A few changes to profiler support in verilog model

- The previous implementation sampled issued instructions.  This would not
take cache misses into account. The new version samples the program counter
in the instruction fetch stage (which will weight blocked instructions more
heavily)
- Make the profiler randomly sample only around every 1 of every 64 instructions
instead of collecting every cycle. This doesn't seem to impact accuracy too much
and makes postprocessing the profile files faster.