sim_core: fixes and reductions

correct a few goofed up opcode descriptions.

get_d5 and get_r5: remove trailing slash on last macro line

add get_vd5: get_vd5 pulls in from get_d5 plus loads from register...
	removes one definate instance of a possible double load, also
	potentially removes double loads during tracing.

get_d5_b3 changed to get_vd5_b3: as all instances use the value of
	reg d.  get_vd5_b3 pulls in from get_vd5.  reduces one definate
	instance for potential of double loads and possibly reducing
	the potential during tracing.

add get_vd5_b3_mask: two instances use b3 as a mask, get_vd5_b3_mask
	pulls in from get_vd5_b3.

add get vh4_k8: get_vh4_k8 pulls in from get_h4_k8, removes the extra
	line to pull in from the register...  removes possible double
	load during tracing.

get_p2_k6 changed to get_vp2_k6: register load was moved into the macro
	as both instances need the value loaded from the register pair.

add get_io5 and get_io5_b3mask: get io5_b3 and get_io5_b3mask pulls in
	from get_io5...  most instances using get_io5_b3 take bit
	number and use it as a mask, get_io5_b3mask does that by default.

get_o12: rcall and rjmp both left shift the value back before using
	the offset...  the macro just calls for one less bit to be
	shifted...  during trace we then make the extra shift as needed.

	modified:   sim/sim_core.c