submodule: move legacy-vme64x-core into fpga-config-space
pexarria5: rerun hdlmake
pexarria5: fix remote reboot
pexarria5: consistently set io standard and termination for all lvdscon pins

Some LVDS pairs had only half of the pin marked as LVDS.
Differential input termination is needed to get high quality input signals.
arria5: use fixed lvds tx clocking
pexaria5: import CPLD project from Jan
quartus projects: re-run hdlmake