DLX executes correctly test_while.asm.

Fixes done:
stage 1 control signals (RF - cw1) must be latched instead of clocked. Also, cw2 expects a clocked signal (otherwise 1 delay cycle is missed):

So, cw1 has been doubled:
CW -> LATCH -> CW1_latched goes to RF stage (tested - if it's not done the register file does not receive correctly the read and write commands)
CW -> REG -> CW1 goes to the pipe
RS1 and RS2 inputs into DLX.vhd have been latched too.

Fixes on PC computation:
PC is managed as a cutted value (i.e. PC/4 is used) internally into the fetch stage, but from the instruction set normal PC (aligned to 32 bit) is used (PC(1
downto 0)="00" always).
So, two bits are added to fetch stage's PC while entering the datapath, and they are removed when exiting as FALLBACK_ADDRESS.