Reconfigure to "stock" Propeller 1 memory map

Restored hub memory to original design, including 32K hub RAM, and full
ROMs including the math tables and Propeller font.  For more usable
memory, it's not hard to go back to the 4K ROM files and hub_mem.v
provided by the Pipistrello version, but I wanted to be able to have the
full functionality of the original chip.

Also:
1) Added a Xilinx-specific Clock-Enable primitive for the video clock
signals rather than the LUT-driven scheme.
2) Modified constraints to connect several IOs to the Nexys4 VGA port in
the same fashion as the Propeller Demo Board, and verified that video
output applications behave correctly.
Modified Xilinx Project file for Nexys4

This file needs to reference the Nexys4 constraints UCF file and
eliminate the Pipistrello reference in order to compile properly.
Final recompiled bitfile

For "Stock" propeller emulation on Artix7/Nexys4 board, including video
output wired as per the Propeller Demo Board.
Merge Andy's changes to Nexys4 directory