ARM: dts: msm: Add num fabrics to the msm8226 target

Add the number of fabrics present to the msm8226 device tree file. Use
this propoerty instead of APIs in code to determine the target type to
arrive at the number of bus fabrics present.

CRs-Fixed: 642345
Change-Id: I299d735b3c37c583b29a5cdb13367af42ccf8cea
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
ARM: dts: msm: Add BKE throttling for A7SS on msm8226

Introduce BKE throttling of A7SS on msm8226 to mitigate delays
experienced by some real time masters on the SOC.

Change-Id: I3971ef0184486fab7dfa4c5ce24ba55cf254cc84
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
ARM: dts: msm: Add pm-qos-latency to GPU dtsi

Currently the code has a fixed CPU latency vote from
the GPU driver. Some targets have different latency
requirements to allow various low latency PC modes.
Allow the CPU latency vote to be programmable based
on target. 701us PM QOS allows the A7 targets select
Low Power Mode which is better in terms of power.
This will help save static leakage of A7 during
graphics use cases.

Change-Id: I38a7ae76a4ebe0c4c98e6bc6d58353989e94c611
Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
ARM: dts: msm8926: Add AB values to the GPU BIMC votes

At least a portion of the GPU's bus usage needs to be taken into
account on low end use cases to prevent underrun for other bus
users.  Add default votes to be taken into account in the BIMC
AB calculation.

Change-Id: I26068027087c0a177a4e0d6a2b15c8859af5c27f
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
Signed-off-by: Gopal G Goberu <ggober@codeaurora.org>
ARM: dts: msm: set maximum voltage after uplift to 1.33V for msm8226

Uplifted APC voltage should not exceed 1.33v according to new voltage plan
for 8x26. Change it to comply with the new plan and still maintain
VDD_APC<=VDD_MX with MX max=1.3375v.

Change-Id: Ia0f137a1ba68680e3b943a6e98575be10689de91
CRs-Fixed: 630579
Signed-off-by: Ke Liu <keliu@codeaurora.org>
msm: pm: Notify secure code of L2 power mode from last core only

Notify secure code L2 low power mode only if the current core is the
last core down. In certain scenarios, its possible that Linux and
secure code have different views of what a last core and could result in
secure code not invalidating a cache when the L2 was placed in a
non-retention mode.

Consider a two core scenario where Core 1 is power collapsed and Core 0
is the last core down setting L2 to be invalidated. Before Core 0 makes
the scm call, its possible that is interrupted to process a secure
interrupt. If the Core 1 wakes up in this time and decides to vote a
different L2 mode, this mode wouldn't be consistent with what Core 0
passes down to secure code when resuming from interrupt handling. In
these cases, the secure code could end up incorrectly invalidating the L2
on warmboot.

Also, the secure code and Linux should have a consistent view of what
last core down is to flush and invalidate L2. To ensure this, acquire a
remote (hardware) spinlock to serialize the last portion of the
power-collapse sequence. The remote spinlock will be released by the
secure code after it acquires its own lock to serialize the power
collapse sequence.

msm: pm: Acquire scm_handoff_lock conditionally

Acquisition of the scm_handoff_lock requires a TrustZone software
image that will release the lock. Without this, a deadlock will
occur since the lock will remain held forever.

Since this lock is only really needed if the qcom,allow-synced-levels
property is specified for the lpm-levels device, conditionally acquire
the lock based on this property. This avoid the TrustZone software
dependency when qcom,allow-synced-levels is not specified.

Change-Id: I8f8f1e4f9bdab6e70ef2a5484faba4e8ce8ac20c
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>