docs: Import 10.2.3 release notes

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nv50/ir: retrieve shadow compare from first arg

This can only happen with texture(samplerCubeShadow, bias), where the
compare will be in the first argument.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
nv50/ir: ignore bias for samplerCubeShadow on nv50

Unfortunately there's no good way to do this on the nv50 shader isa.
Dropping the bias seems preferable to doing the compare post-filtering.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
nvc0/ir: do quadops on the right texture coordinates for TXD

handleTEX moves the layer as the first argument. This makes sure that
the quadops deal with the texture coordinates.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
nvc0/ir: use manual TXD when offsets are involved

Something about how we're implementing offsets for TXD is wrong, just
flip to the generic quadop-based implementation in that case.

This is the minimal fix appropriate for backporting.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
nvc0/ir: fill offset in properly for TXD

Apparently TXD wants its offset differently than TEX, accepting it in
the upper bits of the layer index. Unclear what happens when this is
combined with indirect sampler indexing.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
i965: Extend compute-to-mrf pass to understand blocks of MOVs

The current compute-to-mrf pass doesn't handle blocks of MOVs.  Shaders
that end with a texture fetch follwed by an fb write are left like this:

0x00000000: pln(8)          g6<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 WE_normal 1Q compacted };
0x00000008: pln(8)          g7<1>F          g4.4<0,1,0>F    g2<8,8,1>F      { align1 WE_normal 1Q compacted };
0x00000010: send(8)         g2<1>UW         g6<8,8,1>F
                            sampler (1, 0, 0, 1) mlen 2 rlen 4              { align1 WE_normal 1Q };
0x00000020: mov(8)          g113<1>F        g2<8,8,1>F                      { align1 WE_normal 1Q compacted };
0x00000028: mov(8)          g114<1>F        g3<8,8,1>F                      { align1 WE_normal 1Q compacted };
0x00000030: mov(8)          g115<1>F        g4<8,8,1>F                      { align1 WE_normal 1Q compacted };
0x00000038: mov(8)          g116<1>F        g5<8,8,1>F                      { align1 WE_normal 1Q compacted };
0x00000040: sendc(8)        null            g113<8,8,1>F
                            render ( RT write, 0, 4, 12) mlen 4 rlen 0      { align1 WE_normal 1Q EOT };

This patch lets compute-to-mrf recognize blocks of MOVs and match them to
instructions (typically SEND) that writes multiple registers.  With this,
the above shader becomes:

0x00000000: pln(8)          g6<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 WE_normal 1Q compacted };
0x00000008: pln(8)          g7<1>F          g4.4<0,1,0>F    g2<8,8,1>F      { align1 WE_normal 1Q compacted };
0x00000010: send(8)         g113<1>UW       g6<8,8,1>F
                            sampler (1, 0, 0, 1) mlen 2 rlen 4              { align1 WE_normal 1Q };
0x00000020: sendc(8)        null            g113<8,8,1>F
                            render ( RT write, 0, 20, 12) mlen 4 rlen 0     { align1 WE_normal 1Q EOT };

which is the bulk of the shader db results:

total instructions in shared programs: 987040 -> 986720 (-0.03%)
instructions in affected programs:     844 -> 524 (-37.91%)
GAINED:                                0
LOST:                                  0

The optimization also applies to MRT shaders that write the same
color value to multiple RTs, in which case we can eliminate four MOVs in
a similar fashion.  See fbo-drawbuffers2-blend in piglit for an example.

No measurable performance impact.  No piglit regressions.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
ilo: fix fence reference counting

The old code was complicated, and was wrong when *ptr is NULL.
nvc0: allocate more space before a counter is configured v2

On nvc0, a counter can up to 6 sources instead of only one
for nve4+. This fixes a crash when a counter uses more than
one source.

V2:
 - add the Reviewed-by

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
gallium: add pipe_screen::get_driver_query_group_info v2

This will be used to get groups of queries required by
GL_AMD_performance_monitor.

V2:
 - add doc to src/gallium/docs/source/screen.rst
 - s/pipe_context/pipe_screen in the commit msg
 - improve commit message

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
gallium: add a group_id field to pipe_driver_query_info v2

V2:
 - make group_id the last field of this struct, this fixes
 drivers which use pipe_driver_query_info like radeon

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
gallium: add util_get_driver_query_group_info

This generic function will be used to get groups of queries.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
gallium: add is_percentage and is_float fields to pipe_driver_query_info

This will be used by GL_AMD_performance_monitor.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
gallium: Add a f32 field to pipe_query_result

This will be used for the GL_FLOAT counter type of
AMD_performance_monitor.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
gallium: replace pipe_driver_query_info::max_value by a union v2

This allows to return different numeric types for queries.

V2:
 - use float instead of double

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
gallium: make pipe_context::begin_query return a boolean

This can be used to check if a query is unable to start.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
mesa/st: implement GL_AMD_performance_monitor v4

This is based on the original patch of Christoph Bumiller.
(source: http://people.freedesktop.org/~chrisbmr/perfmon.diff)

Drivers must implement get_driver_query_group_info and
get_driver_query_info in order to enable this extension.

V2: (Samuel Pitoiset)
 - fix compilation
 - improve the original code
 - rewrite some parts of the original code

V3:
 - do not use pipe_driver_query_info::min_value which is always set to 0

V4:
 - only enable AMD_performance_monitor if the driver implements
 pipe_screen::get_driver_query_group_info and get_driver_query_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
svga: implement pipe_screen::get_driver_query_group_info v3

This enables GL_AMD_performance_monitor for svga.

V2:
 - s/pipe_context/pipe_screen in the commit msg

V3:
 - use util_get_driver_query_group_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
freedreno: implement pipe_screen::get_driver_query_group_info v3

This enables GL_AMD_performance_monitor for freedreno.

V2:
 - s/pipe_context/pipe_screen in the commit msg

V3:
 - use util_get_driver_query_group_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
radeon: implement pipe_screen::get_driver_query_group_info v3

This enables GL_AMD_performance_monitor for radeon.

V2:
 - s/pipe_context/pipe_screen in the commit msg

V3:
 - use util_get_driver_query_group_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>