Power: add an API to log wakeup reasons

Add API log_wakeup_reason() and expose it to userspace via sysfs path
/sys/kernel/wakeup_reasons/last_resume_reason

Change-Id: I81addaf420f1338255c5d0638b0d244a99d777d1
Signed-off-by: Ruchi Kandoi <kandoiruchi@google.com>
POWER: fix compile warnings in log_wakeup_reason

Change I81addaf420f1338255c5d0638b0d244a99d777d1 introduced compile
warnings, fix these.

Change-Id: I05482a5335599ab96c0a088a7d175c8d4cf1cf69
Signed-off-by: Ruchi Kandoi <kandoiruchi@google.com>
Power: Add guard condition for maximum wakeup reasons

Ensure the array for the wakeup reason IRQs does not overflow.

Change-Id: Iddc57a3aeb1888f39d4e7b004164611803a4d37c
Signed-off-by: Ruchi Kandoi <kandoiruchi@google.com>
Power: Changes the permission to read only for sysfs file /sys/kernel/wakeup_reasons/last_resume_reason

Change-Id: If25e8e416ee9726996518b58b6551a61dc1591e3
Signed-off-by: Ruchi Kandoi <kandoiruchi@google.com>
ARM: dts: msm: add support for qseecom bus scaling for 8074, 8226 and 8610

To support qseecom bus scaling, ab & ib values are changed to set four
bandwidth levels: "INACTIVE, LOW, MEDIUM and HIGH" with corresponding
bus bandwidth of {0M, 0M, 150M, 492M}; and the flag of support-bus-scaling
is also set for apq8074, msm8226 and 8610.

Change-Id: I15350619143094d280ebc1e3717418285063448d
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Shruthi Krishna <skrish@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
ARM: dts: msm: add frequency to corner mappings for msm8226v2
Add frequency to corner mappings for turbo fuse corner frequencies in 1.2G and 1.4G speedbin tables which located at msm8226v2
clock-a7 device tree node.

1.2G/1.4G msm8226v2 arts can receive a dynamic quotient adjustment to scale the CPR target quotient used for each corner, this ensure these parts receive power saving when running at turbo frequencies below the maximum possible turbo frequency.

Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
ARM: dts: msm: use ordered workqueue only when specified

Use alloc_ordered_workqueue function to queue work only
when specified from the dtsi node for the corresponding led.

Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
ARM: gic: use a private mapping for CPU target interfaces

The GIC interface numbering does not necessarily follow the logical
CPU numbering, especially for complex topologies such as multi-cluster
systems.

Fortunately we can easily probe the GIC to create a mapping as the
Interrupt Processor Targets Registers for the first 32 interrupts are
read-only, and each field returns a value that always corresponds to
the processor reading the register.

Initially all mappings target all CPUs in case an IPI is required to
boot secondary CPUs.  It is refined as those CPUs discover what their
actual mapping is.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Blechd0se <alex.christ@hotmail.de>
msm: rq_stats: Use cpufreq API to get the current frequency

Since the acpuclock APIs are deprecated, use the cpufreq to
get the current frequency of CPUs to calculate the cpu
normalized load value.

Change-Id: I6e381d584d6725ef964bad86c835d44f3046e9c3
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/msm_rq_stats.c

Conflicts:
	arch/arm/mach-msm/msm_rq_stats.c
msm: rq_stats: Fix wrong usage of cpufreq_quick_get()

cpufreq_quick_get() returns frequency in KHz, which is exactly what
cur_freq expect. Remove the wrong multiplication.

CRs-fixed: 645518
Change-Id: Ia8b080a188023964f5eee77c8586828097d11ad4
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
Input: Send events one packet at a time

On heavy event loads, such as a multitouch driver, the irqsoff latency
can be as high as 250 us.  By accumulating a frame worth of data
before passing it on, the latency can be dramatically reduced.  As a
side effect, the special EV_SYN handling can be removed, since the
frame is now atomic.

This patch adds the events() handler callback and uses it if it
exists. The latency is improved by 50 us even without the callback.

Change-Id: Iebd9b1868ae6300a922a45b6d104e7c2b38e4cf5
Cc: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Benjamin Tissoires <benjamin.tissoires@enac.fr>
Tested-by: Ping Cheng <pingc@wacom.com>
Tested-by: Sedat Dilek <sedat.dilek@gmail.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Henrik Rydberg <rydberg@euromail.se>

Input: Improve the events-per-packet estimate

The events-per-packet estimate has so far been used by MT devices
only. This patch adjusts the packet buffer size to also accomodate the
KEY and MSC events.  Keyboards normally send one or two keys at a
time. MT devices normally send a number of button keys along with the
MT information.  The buffer size chosen here covers those cases, and
matches the default buffer size in evdev. Since the input estimate is
now preferred, remove the special input-mt estimate.

Reviewed-and-tested-by: Ping Cheng <pingc@wacom.com>
Tested-by: Benjamin Tissoires <benjamin.tissoires@enac.fr>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Henrik Rydberg <rydberg@euromail.se>
ARM: mm: rename jump labels in v7_flush_dcache_all function

This patch renames jump labels in v7_flush_dcache_all in order to define
a specific flush cache levels entry point.

TODO: factor out the level flushing loop if considered worthwhile and
      define the input registers requirements.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
Signed-off-by: Paul Reioux <reioux@gmail.com>
ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API

When a CPU is hotplugged out caches that reside in its power domain
lose their contents and so must be cleaned to the next memory level.

Currently, __cpu_disable calls flush_cache_all() that for new generation
processor like A15/A7 ends up cleaning and invalidating all cache levels
up to Level of Coherency, which includes the unified L2.

This ends up being a waste of cycles since the L2 cache contents are not
lost on power down.

This patch updates __cpu_disable to use the new LoUIS API cache operations.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
Signed-off-by: Paul Reioux <reioux@gmail.com>
ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API

The ARMv7 processor setup function __v7_setup() cleans and invalidates the
CPU cache before enabling MMU to start the CPU with a clean CPU local cache.

But on ARMv7 architectures like Cortex-[A15/A8], this code will end
up flushing the L2 caches(up to level of Coherency) which is undesirable
and expensive. The setup functions are used in the CPU hotplug scenario too
and hence flushing all cache levels should be avoided.

This patch replaces the cache flushing call with the newly introduced
v7 dcache LoUIS API where only cache levels up to LoUIS are cleaned and
invalidated when a processors executes __v7_setup which is the expected
behavior.

For processors like A9 and A5 where the L2 cache is an outer one the
behavior should be unchanged.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
Signed-off-by: Paul Reioux <reioux@gmail.com>
cpufreq: Remove unnecessary initialization of a local variable

Remove an unnecessary initializer for the 'ret' variable in
__cpufreq_set_policy().

[rjw: Modified the subject and changelog slightly.]
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Signed-off-by: Blechd0se <alex.christ@hotmail.de>
Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
more faster wake lock

Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
Bump kernel revision due to additional commits

Change-Id: I3aaa5196ef8d17fe41276532ddc60c40362dc3d6
Revert "more faster wake lock"

This reverts commit 19305b886c8853c26ae84ddd2b75bff997d84e00.
Bump kernel revision due to reverted/removed commits (wakelock issue)

Change-Id: Ia17f575ede3e3277b7e15d81d0685d89bea6b400