update documentation for ShiftRegister
document optional enable for shift register in manual
Fix UIntToOH for expicitly-specified non-pow2 widths
Add min/max operators to Num

The dynamic cast is correct but unfortunate--anyone know how to avoid it?
Fix bit insertion for insufficiently-wide indices
Merge branch 'master' of github.com:ucb-bar/chisel
Fix scala compiler warning
Update canonical test outputs

Commit 686ecc790e8e6f5e290ffeffea2e5b6aae173663 failed to do so.
Fixed variable-length hashes for jackhammer dump files
Updated tested behavior to more closely match Verilog timing.
Merge branch 'master' into new_new_tester
Updating internal tests to reflect new tester behavior.
Passes all internal tests.
Support seeding random number generator with arg to init()

Passing 0/false disables randomization, as before.
Passing a nonzero value seeds the LFSR.
Use CXX to specify the "g++" version in the environment.
Merge pull request #224 from zhemao/shiftreg-doc

Update documentation for ShiftRegister
Added --vcdMem option for dumping Memory/ROM state.

   Before this behavior was the default with no option to turn it off.
Merge pull request #228 from ccelio/master

Added --vcdMem option for dumping Memory/ROM state.
Fix long RSH by adding dat_t::operator[](size_t)

I'm not entirely sure if this is the correct way to fix this, but it
seems to be the least intrusive way of going about it.  For some
reason the multi-word RSH code was emiting some operators that aren't
defined.  I couldn't figure out why, so I just went ahead and added
the operator in.
Fix a code-gen issue related to reinterpret_cast

This is actually pretty straight-forward, a single "&" appears to have
simply been dropped from the following commit:

commit a05bc928e0835b2022d87955226677e381ff9abc
Author: Andrew Waterman <waterman@eecs.berkeley.edu>
Date:   Sun May 25 21:46:26 2014 -0700

    Support sparse ROMs

    These are useful both for speeding up combinational logic in C++
    and for attaining better synthesis QoR.

in case anyone is interested, the following code triggers the error

import Chisel._;
object Torture {
  def main(args: Array[String]): Unit = {
    chiselMain(args, () => Module(new Torture()));
  }
}
class Torture extends Module {
  class IO extends Bundle {
    val in0 = Bits(INPUT, width=65);
    val in1 = Bits(INPUT, width=65);
    val out0 = Bits(OUTPUT, width=65);
  }
  val io = new IO();
  val io_in0 = Bits(width = 65);
  io_in0 := io.in0;
  val io_in1 = Bits(width = 65);
  io_in1 := io.in1;
  val Torture2 = Bits(width = 65);
  Torture2 := io_in0 / io_in1;
  io.out0 := Torture2;
}

I'm not sure that the emitted code is actually wrong, as I don't know
much about what's going on here.  In other words, it could be correct
in this sparse ROM case, I just don't know how to even generate one.
This passes through the rest of my torture tester tests, so hopefully
it's OK?