axi_dmac: Delay up_ack by one clock cycle

The read data also becomes available only with a delay of one clock cycle,
sending the ack too early will result in bogus register reads.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
axi_ad9361: Fix data order in 1tx mode

Make sure that we send out the data in the correct order in 1tx mode.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
axi_dmac: Fix Vivado warnings

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>