hdl/modules/fmc_adc_common/fmc_adc_data.vhd: add reset to FIFO

As of now, we are using an updated version of the general-cores
repository.

One of the modifications is the absence of the coregen stuff used
for generating FIFOs and RAMs. Now, Xilinx primitives are used for that
and a wrapper is provided to customize it.
hdl/modules/dbe_common/*: add generic pipeline stages in reset_synch
hdl/ip_cores/general-cores: update submodule reference
hdl/ip_cores/dsp-cores: update submodule reference