Add testLit168 for issue #168. Requires investigation.
Add explicit test for LitAsPort168.
Merge branch 'lit168' into litport168

Conflicts:
	src/test/scala/StdlibTest.scala
Fix for Issue #168 - lit as port breaks chisel.

Specifically allow UInt Literal TypeNodes.
This could possibly be restricted to top level nodes.
Fix issue #168 - lit as port breaks chisel - flag it as a ChiselError.
Wrap LitAsPort in try/catch since we now expect it to fail and require ChiselErrors be non-empty to pass.
Merge branch 'master' into litport168
Merge branch 'master' into litport168
Merge branch 'master' into litport168
Update error message.
Merge pull request #311 from ucb-bar/litport168

Litport168 - fix for #168 - lit as port breaks chisel.