code clean up: remove trailing whitespaces
code clean up: remove empty lines at end of files
mor1kx_execute_alu: remove unneeded resets on divider and multiplier
mor1kx_execute_alu: fix comment on a_eq_b
mor1kx_pic: remove unneeded registering on spr_picsr in LEVEL mode
mor1kx_ctrl_cappuccino: simplify, optimize and clean up
store_buffer: fix full_o signaling

The full_o signal would assert *before* the last free spot in
the FIFO would be written, instead of *after*.
This fixes this.
Credits to Olof Kindgren for suggesting this solution.
bus_if_wb32: change module definition to verilog 2001 style
bus_if_wb32: use upper case for parameters
Multicore: Add core identifier

The core identifier can be read from SPR group 0 (system) at address
128 (newly assigned). Furthermore it is possible to read the number of
processor cores in a cluster via register 129. Both can apparently not
be written.

The registers are set via ports, which allow easier use in verilated
models or similar.
mor1kx_ctrl_cappuccino: fix spr_access_ack[`OR1K_SPR_SYS_BASE] and clean up DEBUGUNIT
mor1kx_pic, mor1kx_ticktimer: use spr_access_i on all spr_addr check
cappuccino/ctrl: left justify generate statements
cappuccino/ctrl: negate external spr units on non access

This ensures that the external spr units can't assert their
acks when they are not accessed (this logic has changed,
earlier they've been allowed to constantly assert ack).

This together with the data negation should be moved to respective
spr units at some point.
Merge branch 'master' into 'withfpu'