m8: remove graphite optimization

Not supported by AOSP toolchains and doesn't seem to have much if any benefit

Signed-off-by: Jake Weinstein <xboxlover360@gmail.com>
ARM: Introduce arch_read_hardware_id

Moving towards device tree and arm single binary refering to
machine descriptor name for hardware id information under
/proc/cpuinfo is not suitable for certain soc vendors. Add a
hook for soc vendors to supply a per-soc hardware read method.

Change-Id: I8d6f77dbb8037c943d58e0d39fcaa9b54366650e
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
ARM: 7587/1: implement optimized percpu variable access

Use the previously unused TPIDRPRW register to store percpu offsets.
TPIDRPRW is only accessible in PL1, so it can only be used in the kernel.

This replaces 2 loads with a mrc instruction for each percpu variable
access. With hackbench, the performance improvement is 1.4% on Cortex-A9
(highbank). Taking an average of 30 runs of "hackbench -l 1000" yields:

Before: 6.2191
After: 6.1348

Will Deacon reported similar delta on v6 with 11MPCore.

The asm "memory clobber" are needed here to ensure the percpu offset
gets reloaded. Testing by Will found that this would not happen in
__schedule() which is a bit of a special case as preemption is disabled
but the execution can move cores.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Conflicts:
	arch/arm/include/asm/Kbuild
	arch/arm/kernel/smp.c

Change-Id: Ie143b692a5eea090e615e86e22df90f6ecd7fc2c
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: lpm_levels: remove rpm handshake in l2_gdhs mode

Remove rpm handshake in l2_gdhs mode and adjust the
latency values for l2_gdhs mode. Add a new dt entry to
inform lpm_levels driver to send sleep votes to rpm.

CRs-fixed: 604873
Change-Id: I9eeae5fada4f84ee2ca2eb9d67707dee1adf56ac
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
msm: lpm_levels: return new idle level to cpuidle framework

Need to return the new idle level to cpuidle framework
but just returned input value argument 'index' which is
not used actually at lpm_cpu_power_select().

CRs-fixed: 601636
Change-Id: Iabd182eeb4fbdc67f4e07b40a1b593471cf8cbdf
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
msm: lpm_levels: fix driver compilation issue

Assigning an unsinged long value to unsinged int is not
correct and it cause driver compilation failure. Fix by
assigning a proper value.

Change-Id: Ia8d214425c3ba07006e748bc74365da6bc22f224
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
msm: lpm: remove redundant assignment

Removed the redundant cpu level is assignment.

Change-Id: I1aecc4f3d1eb55cd9e057c82f63b8f145401c0fc
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
ARM: add cpufreq transiton notifier to adjust loops_per_jiffy for smp

If CONFIG_SMP, cpufreq skips loops_per_jiffy update, because different
arch has different per-cpu loops_per_jiffy definition.

Change-Id: I3bfdf800784c9c494f873de096e3a1972f14f358
Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: MassStash <MassStash@gmail.com>
ARM: 7653/2: do not scale loops_per_jiffy when using a constant delay clock

When udelay() is implemented using an architected timer, it is wrong
to scale loops_per_jiffy when changing the CPU clock frequency since
the timer clock remains constant.

The lpj should probably become an implementation detail relevant to
the CPU loop based delay routine only and more confined to it. In the
mean time this is the minimal fix needed to have expected delays with
the timer based implementation when cpufreq is also in use.

Change-Id: I75f66afe0cd4851031c71c1ebd522b402bb0a788
Reported-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: MassStash <MassStash@gmail.com>
ARM: 7685/1: delay: use private ticks_per_jiffy field for timer-based delay ops

Commit 70264367a243 ("ARM: 7653/2: do not scale loops_per_jiffy when
using a constant delay clock") fixed a problem with our timer-based
delay loop, where loops_per_jiffy is scaled by cpufreq yet used directly
by the timer delay ops.

This patch fixes the problem in a more elegant way by keeping a private
ticks_per_jiffy field in the delay ops, independent of loops_per_jiffy
and therefore not subject to scaling. The loop-based delay continues to
use loops_per_jiffy directly, as it should.

Change-Id: I675a5089c2156c01e7c2e151c7be2795cf965091
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: MassStash <MassStash@gmail.com>
tracing: Have tracing_off() actually turn tracing off

A recent update to have tracing_on/off() only affect the ftrace ring
buffers instead of all ring buffers had a cut and paste error.
The tracing_off() did the exact same thing as tracing_on() and
would not actually turn off tracing. Unfortunately, tracing_off()
is more important to be working than tracing_on() as this is a key
development tool, as it lets the developer turn off tracing as soon
as a problem is discovered. It is also used by panic and oops code.

This bug also breaks the 'echo func:traceoff > set_ftrace_filter'

Change-Id: Ib170c6356d8190551f7df048fd6e1c6c4c89b999
Cc: <stable@vger.kernel.org> # 3.4
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
msm: vidc: Fix various decoder downscalar issues

Queue output buffers without extradata to Venus.
Venus is returning UPSCALE_NOT_SUPPORTED error when
output2 size is bigger than output size. This change
suppresses this error as it is not fatal.

Change-Id: I8a3f708092b131400b88828f6c1a684f08b3f18a
Signed-off-by: Praneeth Paladugu <ppaladug@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
qcom-cpufreq: Fix frequency table registration

CPUfreq device is the provider of CPU frequency table, and
it should always keep track of freq tables for every CPU itself.
cpufreq_frequency_get_table() is an API for frequency table user.
qcom-cpufreq should not use this API to obtain CPU freq table in
the init function. Otherwise, the following sequence will lead to init
failure.

Assume CPU 0 and 1 are under control of same policy and online. Say
policy->cpu is CPU 0.

1) Hot unplug CPU0
   update_policy_cpu() will transfer ownership of policy to CPU1
   cpufreq_frequency_table_update_policy_cpu() is called during
   the process to set CPU1's freq table to be the same as CPU0's freq
   table. CPU0's freq table is now NULL.
2) Hot unplug CPU1
   All CPUs in policy are now offline.
3) Hot plug in CPU0
   cpufreq_driver->init() is called for initialization. If this init
   function calls cpufreq_frequency_get_table() on CPU0, the result
   will be NULL.

Current qcom-cpufreq checks return value of cpufreq_frequency_get_table()
and returns an error in init.

Remove the usage of cpufreq_frequency_get_table() and fill in frequency
table for policy->cpu in msm_cpufreq_init().

Change-Id: I2d41af776938c31b4444c9f280a341dd1bed1548
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
Signed-off-by: MassStash <MassStash@gmail.com>
ARM: net: JIT compiler for packet filters enabled by default
optimize slack
msm: lpm_levels: Fix incorrect computation of next wakeup time

The next event timer wakeup was incorrectly computed when the hard timer
event doesn't exist. Fix by ensuring the next wakeup is computed only
when a timer event is valid

Change-Id: I40c1f372f84d8f43b2101e37dcfb592193d4b2e0
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: mpm-of: fix for "cxo_lpm_clk is unbalanced" slowpath warning.

The variable xo_enabled needs protection. It might get called
simultaneously from suspend and mpm worker thread context.
Added a mutex to prevent this.

WARNING: at kernel/arch/arm/mach-msm/clock.c:411 clk_disable+0xc8/0x150()
cxo_lpm_clk is unbalanced
Modules linked in: adsprpc texfat(PO) mwlan_aarp(PO)
[<c010d24c>] (unwind_backtrace+0x0/0x138) from [<c01a0408>]
(warn_slowpath_common+0x4c/0x64)
[<c01a0408>] (warn_slowpath_common+0x4c/0x64) from [<c01a04b4>]
(warn_slowpath_fmt+0x30/0x40)
[<c01a04b4>] (warn_slowpath_fmt+0x30/0x40) from [<c011a068>]
(clk_disable+0xc8/0x150)
[<c011a068>] (clk_disable+0xc8/0x150) from [<c0180568>]
(msm_mpm_sys_low_power_modes+0x28/0x84)
[<c0180568>] (msm_mpm_sys_low_power_modes+0x28/0x84) from [<c0180768>]
(msm_mpm_work_fn+0x1c/0x5c)
[<c0180768>] (msm_mpm_work_fn+0x1c/0x5c) from [<c01b9568>]
(process_one_work+0x128/0x490)
[<c01b9568>] (process_one_work+0x128/0x490) from [<c01b9c14>]
(worker_thread+0x164/0x35c)
[<c01b9c14>] (worker_thread+0x164/0x35c) from [<c01be9a8>]
(kthread+0x88/0x94)
[<c01be9a8>] (kthread+0x88/0x94) from [<c0107a04>]
(kernel_thread_exit+0x0/0x8)
---[ end trace d18a7d72e45b272f ]---
------------[ cut here ]------------
WARNING: at kernel/arch/arm/mach-msm/clock.c:436 clk_unprepare+0xac/0xd4()
cxo_lpm_clk is unbalanced (prepare)
Modules linked in: adsprpc texfat(PO) mwlan_aarp(PO)
[<c010d24c>] (unwind_backtrace+0x0/0x138) from [<c01a0408>]
(warn_slowpath_common+0x4c/0x64)
[<c01a0408>] (warn_slowpath_common+0x4c/0x64) from [<c01a04b4>]
(warn_slowpath_fmt+0x30/0x40)
[<c01a04b4>] (warn_slowpath_fmt+0x30/0x40) from [<c011aa78>]
(clk_unprepare+0xac/0xd4)
[<c011aa78>] (clk_unprepare+0xac/0xd4) from [<c0180570>]
(msm_mpm_sys_low_power_modes+0x30/0x84)
[<c0180570>] (msm_mpm_sys_low_power_modes+0x30/0x84) from [<c0180768>]
(msm_mpm_work_fn+0x1c/0x5c)
[<c0180768>] (msm_mpm_work_fn+0x1c/0x5c) from [<c01b9568>]
(process_one_work+0x128/0x490)
[<c01b9568>] (process_one_work+0x128/0x490) from [<c01b9c14>]
(worker_thread+0x164/0x35c)
[<c01b9c14>] (worker_thread+0x164/0x35c) from [<c01be9a8>]
(kthread+0x88/0x94)
[<c01be9a8>] (kthread+0x88/0x94) from [<c0107a04>]
(kernel_thread_exit+0x0/0x8)
---[ end trace d18a7d72e45b2730 ]---

CRs-fixed: 596765
Change-Id: Ibe685e8f37eb63c4e9e9d3434719985f33c63376
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
msm: lpm_levels: fix incorrect mode select with next event time

Based on the next event timer value the best power mode will get
selected but there is a mismatch in calculation of selecting
the best mode. This change will fix that and selects the correct
mode based on the next wakeup time.

CRs-fixed: 611794
Change-Id: I31270e62b04e7a97afa1c9b0c45069ad82d1a9b0
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
msm: lpm_levels: update suspend stats counters and time

suspend stats in the debug pm stats are not getting updated as
suspend stats in the suspend wake path is missing. This change
will add and update the suspend stats in the suspend wake path.

Change-Id: I3b47511afb75926e51e82fc83929f405404fbf07
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/msm-pm.c
msm: pm: Notify secure code of L2 power mode from last core only

Notify secure code L2 low power mode only if the current core is the
last core down. In certain scenarios, its possible that Linux and
secure code have different views of what a last core and could result in
secure code not invalidating a cache when the L2 was placed in a
non-retention mode.

Consider a two core scenario where Core 1 is power collapsed and Core 0
is the last core down setting L2 to be invalidated. Before Core 0 makes
the scm call, its possible that is interrupted to process a secure
interrupt. If the Core 1 wakes up in this time and decides to vote a
different L2 mode, this mode wouldn't be consistent with what Core 0
passes down to secure code when resuming from interrupt handling. In
these cases, the secure code could end up incorrectly invalidating the L2
on warmboot.

Also, the secure code and Linux should have a consistent view of what
last core down is to flush and invalidate L2. To ensure this, acquire a
remote (hardware) spinlock to serialize the last portion of the
power-collapse sequence. The remote spinlock will be released by the
secure code after it acquires its own lock to serialize the power
collapse sequence.

msm: pm: Acquire scm_handoff_lock conditionally

Acquisition of the scm_handoff_lock requires a TrustZone software
image that will release the lock. Without this, a deadlock will
occur since the lock will remain held forever.

Since this lock is only really needed if the qcom,allow-synced-levels
property is specified for the lpm-levels device, conditionally acquire
the lock based on this property. This avoid the TrustZone software
dependency when qcom,allow-synced-levels is not specified.

Change-Id: I8f8f1e4f9bdab6e70ef2a5484faba4e8ce8ac20c
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>

Conflicts:
	arch/arm/boot/dts/msm8610-v1-pm.dtsi
	arch/arm/boot/dts/msm8610-v2-pm.dtsi
	arch/arm/mach-msm/msm-pm.c