Allow ADC5g to run in high bandwidth mode at 5Gsps

Previously, when using the ADC5g at [interleaved] sample rates between 4800 Msps and 5400 Msps the only compatible MMCM parameters required the MMCM to operate in low bandwidth mode. This resulted in poor performance, with glitches on data capture hard to reliably calibrate out with IODELAYs and clock phase rotation.
This commit changes the ISERDES used in the interface to operate in OVERSAMPLE (rather than NETWORKING) mode, which allows them to be driven by a clock half the rate as was previously required. Removing the need for the faster clock means that the MMCM can be configured in high bandwidth mode at all clock frequencies, and performs much more reliably at 5 Gsps.
This change has only been implemented for the ROACH2 demux 1:1 version of the interface (which I think is probably the only one that caused problems).
Also changed the SERDES blocks to use the DDLY (rather than D) input, which, according to the Xilinx data sheet is the dedicated input from an IODELAY (rather than an IOB)