Initial submission.

add: initial submission.  Contains the root of a C# emulator, along with a C++ SDL2 sample project and SDL2 itself.
Add utilities, basic bootup sequence.

add: Utils.h, Exception, Janitor

change: emulator now loads Tetris ROM and sets SDL window title appropriately
Add custom build step to copy output executable.

add: custom build step that should copy the executable to the working directory.  First time with method instead of post-build steps (which only run when there is something to compile/link), it seems flaky.
Add SDL2 prebuilts to repo.

add: prebuilt release SDL2.lib/dll in external and workingdir
Emulator start - add Cpu/Memory classes.

add: Cpu, Memory classes

add: header to define memory-mapped registers; will probably change a bit
add: basic execution flow with a handful of opcodes; will undoubtedly be refactored
change: go back to a normal post-build step with the flaws that entails; the custom build step was very wonky and would cause infinite rebuild loops
More opcodes, basic flags, HRAM support, DIV register.

add: more opcode implementations - will definitely want to refactor/bunch some stuff, still thinking about what the best way to do that might be

add: basic flags register manipulation
add: total executed opcodes count
add: HRAM support
add: DIV register
Add test ROMs along with source.

add: test GB-Z80 ROMS, source, and documentation from Blargg
Protoype template-based opcode implementations.

change: prototype a more interesting way to implement opcodes using compile-time code generation.  The opcode values are constexpr, so it's possible to get the compiler to parse out the right bits and generate the right unique implementation for each opcode.
More template-based LD opcodes.

add: LD_0_3__1
add: *GetReg*-based template test to have a single function aliasing a register, to be used by both the read and write Impls.  The unspecialized template method can call the GetReg method (which will not have a specialization for any indirect addressing), and an Impl specialization could be made to handle said indirect addressing.
More template-based LD opcodes.

add: LD_0_3__6__0_3__E
Cleanup.

remove: unused line.
Add missing SDL2main.lib.

add: SDL2main.lib
More opcode support.

add: more LD, LDI, LDD; DEC; CP; JR
Extremely basic/hacked disassembler/debugger, more opcode support.

add: SafeRead8() to Memory for the debugger, to handle reads to invalid addresses
fix: JR was fetching the offset conditionally, which is bad
add: a bit more flag manipulation scaffolding, to be refactored at some point
add: INC, ADD, HALT (preliminary halt support)
Break apart emulator.cpp into separate files.

change: break apart code into separate files.
Create README.md
More cleanup, add minimal debugger state (stepping/running).

change: reimplement old opcodes using new template-based stuff (INC, DEC)
add: single-stepping and running debugger modes
change: moving more functions/cleanup
More micro-opcode refactors.

change: refactored LD, illegal opcodes
change: debugger now breaks before actual execution of instruction

Still some refactoring to do but I will wait a bit to do that, until the test ROM runs, to use it as a benchmark and make sure I'm not breaking anything.
More CPU/memory implementation, refactoring.

add: VRAM
add: read-only memory-mapped registers (implementation to be revised)
change: Memory::SafeRead8() no longer relies on exceptions being thrown, makes debugging much easier
change: refactor micro-opcode templates to make them simpler/more reusable
add: AND, XOR, more CALLs, SUB, LDH, LD; extended opcodes RR, SRL
fix: JR bug where negative displacements were treated as unsigned
fix: bug where Zero flag was being incorrectly set from value in A instead of actual operation result after ADD and SUB
add: memory-mapped registers LCDC, SCY, SCX, LY, BGP, OBP0, OBP1
add: DebugCheckForKeypress()
More implementation work.  Now passes Blargg's test 06!

add: rudimentary MBC1 support that does not support bank switching yet, it just maps bank 01
add: support for printing out of the serial port
add: STOP, ADD, ADC, RL, RET, RR, LD, JP, XOR
add: SB, SC, NR12, NR13, NR1, KEY1 memory-mapped registers