mesa: trim down some #includes
mesa: fix UNCLAMPED_FLOAT_TO_UBYTE() macro for MSVC

MSVC replaces the "F" in "255.0F" with the macro argument which leads
to an error.  s/F/FLT/ to avoid that.

It turns out we weren't using this macro at all on MSVC until the
recent "mesa: Drop USE_IEEE define." change.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
u_vbuf: simple whitespace fix
radeonsi: Simplify si_dma_copy_tile function

No functional change intended.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
glsl: mark variable as loop constant when it is set read only

Patch modifies is_loop_constant() to take advantage of 'read_only' bit
in ir_variable to detect a loop constant. Variables marked read-only
are loop constant like mentioned by a comment in the function.

v2: remove unnecessary comment (Francisco)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82537
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
glsl: allow precision qualifier on sampler arrays

If a precision qualifer is allowed on type T, it should be allowed
on an array of T.  Refactor the check to ensure this is the case.

(Fixes failures in WebGL conformance test 'gl-min-textures')

Signed-off-by: Frank Henigman <fjhenigman@google.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
ilo: update genhw headers

Add some new registers and some tweaks.  The changes that affect ilo are

 GEN6_REG_HS_INVOCATION_COUNT -> GEN7_REG_HS_INVOCATION_COUNT
 GEN6_REG_DS_INVOCATION_COUNT -> GEN7_REG_DS_INVOCATION_COUNT
 GEN6_COND_NORMAL             -> GEN6_COND_NONE
ilo: add a new disassembler

The old disassembler was modified from i965's.  It is as much work as doing a
new one to keep it up-to-date, which also requires copying more headers over.

The outputs of this new disassembler should match i965's as closely as
possible.
scons: add /dynamicbase and /nxcompat to MSVC linkflags

This builds the opengl DLLs with address layout space randomization
(ASLR) and data execution prevention (DEP) for better security.

Reviewed-by: Kurt Daverman <krd@vmware.com>
scons: add /dynamicbase and /nxcompat to MinGW linkflags

Just like b26503b196d51dc46c815e241343e42ab30e8d66 for MSVC.
radeon/video: use more of the common buffer code v2

In preparation to using buffers clears with the hw engine(s).

v2: split out flipping to using hw buffer clears.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeon/video: use the hw to initial clear the buffers

Less CPU overhead and avoids contention over CPU accessible memory on startup.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
radeon/uvd: use PIPE_USAGE_STAGING for msg&fb buffers

That better matches the actual userspace use case, the
kernel will force it to VRAM if the hardware requires it.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
i965: Implement GL_PRIMITIVES_GENERATED with non-zero streams.

So far we have been using CL_INVOCATION_COUNT to resolve this query but this
is no good with streams, as only stream 0 reaches the clipping stage.

From ARB_transform_feedback3:

"When a generated primitive query for a vertex stream is active, the
 primitives-generated count is incremented every time a primitive emitted to
 that stream reaches the Discarding Rasterization stage (see Section 3.x)
 right before rasterization. This counter is incremented whether or not
 transform feedback is active."

Unfortunately, we don't have any registers that provide the number of primitives
written to a specific stream other than the ones that track the number of
primitives written to transform feedback in the SOL stage, so we can't
implement this exactly as specified.

In the past we implemented this feature by activating the SOL unit even if
transform feeback was disabled, but making it so that all buffers were
disabled and it only recorded statistics, which gave us the right semantics
(see 3178d2474ae5bdd1102fb3d76a60d1d63c961ff5). Unfortunately, this came with
a significant performance impact and had to be reverted.

This new take does not intend to implement the exact semantics required by
the spec, but improves what we have now, since now we return the primitive
count for stream 0 in all cases. With this patch we use
GEN7_SO_PRIM_STORAGE_NEEDED to resolve GL_PRIMITIVES_GENERATED queries
for non-zero streams. This would return the number of primitives written
to transform feedback for each stream instead. Since non-zero streams are
only useful in combination with transform feedback this should not be too
bad, and the only case that I think we would not be supporting would be
the one in which we want to use both GL_PRIMITIVES_GENERATED and
GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN on the same non-zero stream to
detect buffer overflow.

This patch also fixes the following piglit test:
arb_gpu_shader5-xfb-streams-without-invocations

This test uses both GL_PRIMITIVES_GENERATED and
GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN queries on non-zero streams, but it
does never hit the overflow case, so both queries are always expected to return
the same value.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
st/mesa: handle failed context creation for core profile

If the glx/wgl state tracker requested a core profile but the gallium
driver did not support some feature of GL 3.1 or later, we were setting
ctx->Version=0 and then failing the assertion in
_mesa_initialize_exec_table().

With this change we check for ctx->Version=0 and tear down the context
and return NULL from st_create_context().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
tgsi/ureg: add ureg_UARL shortcut
mesa/gallium: API settings / rasterization rules

Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
radeon/softpipe/llvmpipe/svga/i915/ilo/freedreno/nv30: use API settings / rasterization rules

v2: compilation fixes by David Heidelberger <david.heidelberger@ixit.cz>
v3: compilation fix by Thermionix <bond711@gmail.com>

Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
nvc0: improve code readability

Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
nv50/nvc0: use API settings / rasterization rules

Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>