spi: xilinx: Move timeout calculation out of the loop

Timeout calculation should be out of the data loop.
This patch increase spi bandwidth for 30%.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
spi: spi-mxc: add defines for clk inactive state for ECSPI

Provide define for the SCLK_CTL field of the config reg of ECSPI.
While at it, oder the defines to improve readability and make
adding more defines easier.

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3

SPI_MODE_3 requires clk high when inactive. The SCLK_CTL
field of the config reg was not configured in case of CPOL.
Fix configuration so that SPI_MODE_3 which uses CPOL configures
the clk line to be high in inactive state.

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
spi: mxc_spi: i.MX6 DL/S have only 4 eCSPI controller

The dual lite and solo variant have only 4 SPI controller.
respect this in the MXC_SPI_BASE_ADRESSES macro

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
am43xx: Add qspi support

Add QSPI definitions and clock configuration support.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
am437x_epos_evm: add SPL API, QSPI, and serial flash support

Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
spi: ti_qspi: Add AM43xx specifics changes

Add AM43xx specific changes.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
spi: ti_qspi: Add delay before xfer for am43xx

Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.

Without this patch, device does not get probed also.
Here is the log.

U-Boot#
U-Boot#
U-Boot#
U-Boot# sf probe 0
SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff
Failed to initialize SPI flash at 0:0
U-Boot# sf probe 0

While with this patch, log is
U-Boot# sf probe 0
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000
U-Boot# sf erase 0 0x80000
SF: 524288 bytes @ 0x0 Erased: OK
U-Boot# mw 81000000 0xdededede 0x40000
U-Boot# sf write 81000000 0 0x40000
SF: 262144 bytes @ 0x0 Written: OK
U-Boot# sf read 82000000 0 0x40000
SF: 262144 bytes @ 0x0 Read: OK
U-Boot# md 0x82000000

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
doc: SPI: Add qspi test details on AM43xx

This shows the log obtained while testing qspi on AM437x  board.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
serial/serial_arc: add work-around of ISS bug

Explanation is in in-lined comment.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Noam Camus <noamc@ezchip.com>
Cc: Tom Rini <trini@ti.com>
serial/serial_arc: switch from {read|write}l to {read|write}b accessors

This is required for proper functionality on big-endian targets.
Memory-mapped registres of ARC UART are not 32-bit words but 8-bit bytes
so on little-endian target either acessor (_l or _b) works fine.
On big-endian only _b accessors works as expected.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Noam Camus <noamc@ezchip.com>
Cc: Tom Rini <trini@ti.com>
axs101: fix dw gmac instantiation for updated dw gmac driver

With accepted change to DW GMAC driver -
92a190aaab3536d695c51e0739f925910eb49889 (net/designware - switch driver
to phylib usage) we need to update this board because
"designware_initialize" now accepts only 2 parameters instead of 4.

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
axs101: change command prompt marker to match marketing name of the board

Proper spelling of the boad marketing name is with upper case.
So changing it from lower case to upper case here.

Cc: Tom Rini <trini@ti.com>

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
arc: fix relocation for big-endian target

In case of little-endian ARC700 instructions (which may include target
address) are encoded as middle-endian. That's why it's required to swap
bytes after read and ten right before write back.

But in case of big-endian ARC700 instructions are encoded as a plain
big-endian. Thus no need for byte swapping.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Tom Rini <trini@ti.com>
cc: Noam Camus <noamc@ezchip.com>
Merge branch 'master' of git://git.denx.de/u-boot-spi
fs/fdos: Remove

We have an unused FAT implementation in fs/fdos, remove.

Signed-off-by: Tom Rini <trini@ti.com>
serial: arc: Convert to use default_serial_puts

Use default_serial_puts() instead of duplicating the implementation.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
common: Remove invalid endianess conversion

do_bootm_standanlone() calls ntohl(images->ep) which is wrong because
endianess conversion has already been done:

do_bootm()
\-do_bootm_states()
  +-bootm_find_os()
  | \-images.ep = image_get_ep();
  |   \-uimage_to_cpu(hdr->ih_ep);
  \-boot_selected_os()
    \-do_bootm_standanlone()

Without this conversion the code works correctly at least on AT91SAM9G45.
On big endian systems there should be no difference after applying this
patch because uimage_to_cpu(x) and ntohl(x) both expand to 'x'.

Signed-off-by: Christian Eggers <ceggers@gmx.de>
driver/ddr: Change Freescale ARM DDR driver to support both big and little endian

Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.

Signed-off-by: York Sun <yorksun@freescale.com>
Driver/ddr: Add support of different DDR base address

DDR base address has been the same from the view of core and DDR
controllers. This has changed for Freescale ARM-based SoCs. Controllers
setup DDR memory in a contiguous space and cores view it at separated
locations.

Signed-off-by: York Sun <yorksun@freescale.com>