Start of DAC BIST code
Add lambda helpers and finish BIST test code.
LFSR calculation of ideal BIST register values.
Bring run_DAC_BIST up to the library and fix some syntax errors.
Predicate is called first so the true vector should be odd.
Byte order in data sheet seems to be backwards.
Have to set_waveform to get the channel filled it.

TODO: on CH B need to fill in A or perhaps waveform mode should take the longer.
Fill in some more functions in Julia wrapper.
Reduce default logging level

--CAR and BRJ
Take the max of channel A or B waveform length. Closes #11.

--CAR and BRJ
Signed integer data is asymmetric: can go to -8192 but only up to 8191

--CAR and BRJ
Lots of improvements to DAC BIST

* return all BIST values in allocated data
* test each bit line in Julia
* move DAC register addresses into constants
* set the controller clock divider
* rewrite the DAC registers for SD and clock divider after resetting in BIST
Fix DAC_MSDMHD_ADDR

Whoops.
Relative libaps2 in julia code.
C++11-compliance on variable-length arrays.
Back to 45 degree tolerance of DAC phase.

Also, no need to be pedantic about reading back the DAC sampling delay (SD).
Enable/disable DAC FIFOs in appropriate places.
Merge branch 'feature/DAC_BIST' into develop