A P3 pin can now be interrupted by using a timer capture interrupt
Pin mappings, pin modes and pin statuses are no longer modified before entering the sleep mode
ACC power pin initialized
Definition of __ENABLE_P3_PIN_INTERRUPTS__
ADC calibration based on TLV registers
Control Register 2 set to 0x49, with ODR = 400 Hz
Active mode is entered before entering low-power mode
Removed use of Hardwareserial
Adapting sketch for panStamp NRG 1.0 module
Serial port configured to 38400 bps, to keep compatibility with most Python tools