AT45DB: fix read functions.

This fixes segfaults on reads (implicit reads on writes too), ouch.
Thanks to The Raven for reporting the problem and testing my patch, and
to Alexander Irenkov for providing a workable fix for it additionally.

There were actually two problems:
1) The loop conditions were bogus which could lead to read errors
   (e.g. on implicit erase verifications).
2) The offset used within the read buffers provided to spi_nbyte_read()
   and memcpy() were not starting at 0 but the offset of the block
   within the flash chip (which has nothing to do with read buffer in
   most cases).

This patch works similarly to Alexander's but is intended to be
more readable.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

git-svn-id: svn://flashrom.org/flashrom/trunk@1792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
sbxxx: Cleanup.

 - Move programmer definition to the top.
 - Rewrite array accesses to use indices instead of using pointer arithmetic.
 - Move length check and opcode extraction to a function.
 - Move IMC parameter handling into existing IMC handling function.
 - Split comparing and resetting the FIFO pointer.

Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>

git-svn-id: svn://flashrom.org/flashrom/trunk@1793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
sbxxx: Add support for new AMD SPI controller.

This patch adds support for the "SPI 100" SPI engine in Yangtze FCHs
(found in Kabini and Temash).

Tested reading/writing on ASRock IMB-A180 and PC Engines' APU board.

Signed-off-by: Wei Hu <wei@aristanetworks.com>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>

git-svn-id: svn://flashrom.org/flashrom/trunk@1794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
sbxxx: Add spispeed parameter.

Allow to set the SPI clock frequency on AMD chipsets with a programmer
parameter. If the parameter is given (and matches a possible value), the
SPI clock is set temporarily. Both registers are restored on programmer
shutdown.

Example: ./flashrom -p internal:spispeed="33 MHz" -V

Possible values for spispeed are "16.5 MHz", "22 MHz", "33 MHz", "66 MHz",
"100 MHZ" and "800 kHz" depending on the chipset generation.

Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>

git-svn-id: svn://flashrom.org/flashrom/trunk@1795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1