llvm-objdump: use portable format specifiers for info.

ARM bots (& others, I think, now that I look) were failing because we
were using incorrect printf-style format specifiers. They were wrong
on almost any platform, actually, just mostly harmlessly so.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215196 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-objdump: add missing % in format specifier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215198 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64] Add an FP load balancing pass for Cortex-A57

For best-case performance on Cortex-A57, we should try to use a balanced mix of odd and even D-registers when performing a critical sequence of independent, non-quadword FP/ASIMD floating-point multiply or multiply-accumulate operations.

This pass attempts to detect situations where the register allocation may adversely affect this load balancing and to change the registers used so as to better utilize the CPU.

Ideally we'd just take each multiply or multiply-accumulate in turn and allocate it alternating even or odd registers. However, multiply-accumulates are most efficiently performed in the same functional unit as their accumulation operand. Therefore this pass tries to find maximal sequences ("Chains") of multiply-accumulates linked via their accumulation operand, and assign them all the same "color" (oddness/evenness).

This optimization affects S-register and D-register floating point multiplies and FMADD/FMAs, as well as vector (floating point only) muls and FMADD/FMA. Q register instructions (and 128-bit vector instructions) are not affected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215199 91177308-0d34-0410-b5e6-96231b3b80d8
[LoopVectorizer] Enable support for floating-point subtraction reductions



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215200 91177308-0d34-0410-b5e6-96231b3b80d8