Instruction decode rewrite
Registers $8 and up are now back in action

After a longer hiatus of only having a 3-bit wide register select signal
for 16 registers, the select signal is now 4-bit wide.

Much rejoice was had in the lands.
Inrease sram memory size to accomodate 512*256 FB
Add helpful debug prints
Add SLT&MASK and Square draw system tests. Passing.
Move constant / alu data mux out from RF to SP.

This saves register bank height * streaming processor muxes.

:D
Reset instruction delay registers & kernel launch
Merge remote-tracking branch 'origin/master' into LX16

Also some other stuff

Conflicts:
	hardware/instruction_decode.vhd