initial empty check-in
Initial commit. AvalonMaster emulator and tests.
Unified source for emulated Avalon and real Avalon.
Parametrized the address width and reduced the emulator address width to 21 bits.
Defined the cache interface.
Using toGet and toPut instead of fifoToGet and fifoToPut.
More Cache work.
Cache reset state and other cache work.
Big cache refactoring.
First complete implementation of the Cache (not tested yet).
Cache now working.
Added delay stages to the Avalon Master Emulator.
Copy&paste error
Prefetch optimizations and Concurrency tests.
Support to ignore cache in a predefined memory region.
Moved MIPS functionality to Processor.bsv.
- Restricted Avalon address access to data-aligned access.
- Now Avalon address is given in terms of data_width multiples.
- Started to implement instruction decoding.
Use new convention in prefetch addresses.
Implemented all user instructions we plan to implement.
More stuff updated to the new memory access convention and FShow#(Instr) test.