writer_ctrl: make fifo and wb interfaces non-registered

The extra latency by the registering of the fifo signals
result in that the fifo count information does not have time
to propagate back when it is used in S_IDLE state.
The extra latency on the wb signals caused cyc&stb to assert
even when the slave deasserts ack.
writer_ctrl: generate 'active' signal from state == S_ACTIVE
writer_ctrl: set state to S_IDLE on reset
add 'busy' and 'irq' functionality

This adds changes the 'enable' register to become a
'control/status' reigister with the following functionality

control write:
bit 0: 1 = enable, 0 = nop
bit 1: 1 = clear irq, 0 = nop
bit 2-31: reserved

status read:
bit 0: busy
bit 1: irq status
bit 2-31: reserved
wb_stream_writer_tb: Remove redundant parameter
Replace wb_ram with wb_bfm_memory in writer tb
Add IRQ test in writer tb
Add transactions plusar
Increase size of FIFO count vector
Fix test bench sequence
writer: add a way to track the current amount of transmitted data

This makes the transaction counter available to the wishbone
interface.