hdl: Changed constraints and signaling, fixed SPI/UART contention

The FPGA, when in SPI flash access mode, has the UART disappear. It should not be
driving the UART signal or the CTS signal. When the SYS_RST is asserted, drive those pins to 'Z'.
libbladeRF, bladeRF-cli: Switch naming convention to BLADERF_CORR_<DEVICE>_<REG>
hdl: Modify phase range for IQ correction.

Modified the phase range of the FPGA IQ corretion to be +/-10 degrees instead of +/-45 degrees.
libbladeRF: Documented correction parameter values