Initial versions of Patrick's SystemC backend.

Need to rationalize various paths.
Remove package statement, add copyright notice.
Add SystemC test driver.cpp
Add support for chisel standard input/output; SystemC test Makefile
More Chiselification of systemc backend and tests.

Add sysctest, check targets to top level Makefile.
Correct mode (turn off execute bit) for SystemC files.
Comment out debug output, fix resource path root.
Update copyright statement.
Remove commented-out code.
Remove targeted arguments in AddFilter test code (before calling
chiselMainTest()
Renamed driver.cpp to AddFilterSysCdriver.cpp

This file is explicitly for testing the SystemC interface using the
AddFilter.scala test file. It is not a generic SystemC driver - that
would be provided by the top-level SystemC code.
Merge branch 'master' into systemc
Merge branch 'master' into systemc
Start conversion from Java to Scala.
Avoid extracting bits that don't exist

Code such as the following

  class test extends Module {
    val io = new Bundle {
      val data = UInt(INPUT, width = 256)
      val offset = UInt(INPUT, width = 10)
      val bit = UInt(OUTPUT, width = 1)
    }

    io.bit := io.data(io.offset)
  }

is capable of extracting bits that don't exist from a wire.  This
translates into an array access in C++ after multi-word expansion
which in this case results in an out-of-bounds access, whic can SEGV.

This patch works around the problem by extending the input to the
nearest power of two and then computing the shift modulo that power of
two.  This eliminates the undefined behavior in C++ but appears to not
match Verilog (which I think specifies these bits read as 0), which is
a bit hairy.

Note that this happens entirely within chisel, essentially relying on
the backends to optimize this away.

This fixes bug #174
Work around a left-shift code gen issue

I don't really understand what's going on here, but this appears to
work around a code gen issue that chisel-torture found a while ago.
It appears that for some reason wordMangle() doesn't do the right
thing when running in non-debug mode, so I just went ahead and worked
around the problem.

I'm pretty sure this is the wrong solution, but I have no idea what
the correct one is.

This fixes chisel bug #239
Finished (initial) conversion from Java to Scala.
Move Java classes into SCWrapper.java in preparation for Java -> Scala conversion.
Rename SCWrapper.java -> SCWrapper.scala
Merge branch 'systemc' into systemcjavatoscala

Convert SCWrapper.java to SCWrapper.scala
Merge branch 'master' into systemc
Restore required trailing semicolon.
initiail commit for new passes: eliminate couter and backannotation remains
split nameAll
Merge branch 'master' of https://github.com/ucb-bar/chisel into rearrange_passes