i965/brw_reg: struct constructor now needs explicit negate and abs values.

We were assuming, when constructing a new brw_reg struct, that the
negate and abs register modifiers would not be present by default in
the new register.

Now, we force explicitly setting these values when constructing a new
register.

This will avoid problems like forgetting to properly set them when we
are using a previous register to generate this new register, as it was
happening in the dFdx and dFdy generation functions.

Fixes piglit test shaders/glsl-deriv-varyings

Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82991
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 8517e665bc4c378e8e7523827090fd1b06abaecd)
glsl: Add gl_MaxViewports to available builtin constants

It seems to have been forgotten during viewports array implementation time.

Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 19e05d68986690cfcdd49de6cfb87d88ad54cd58)
linker: Wrap access of producer_var with a NULL check

producer_var could be NULL if consumer_var is not NULL and
consumer_is_fs is false.  This will occur when the producer is NULL and
the consumer is the geometry shader for a program that contains only a
geometry shader.  This will occur starting with the next patch.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: pavol@klacansky.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82585
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 5eca78a00a5de442aaf541a1095d5cfa6b4f45de)
Nominated-by: Ian Romanick <ian.d.romanick@intel.com>
linker: Assign varying locations geometry shader inputs for SSO

Previously only geometry shader outputs would be assigned locations if
the geometry shader was the only stage in the linked program.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: pavol@klacansky.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82585
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit a909b995d95892798a189818454905fdefd4bc9b)
Nominted-by: Ian Romanick <ian.d.romanick@intel.com>
i965: Require pixel alignment for GPU copy blit

The blitter will start at a pixel's natural alignment. For PBOs, if the
provided offset if not aligned, bits will get dropped.

This change adds offset alignment check for src and dst, kicking back if
the requirements are not met.

The change is based on following verbiage from BSPEC:
 Color pixel sizes supported are 8, 16, and 32 bits per pixel (bpp).
 All pixels are naturally aligned.

Found in the following locations:
page 35 of intel-gfx-prm-osrc-hsw-blitter.pdf
page 29 of ivb_ihd_os_vol1_part4.pdf
page 29 of snb_ihd_os_vol1_part5.pdf

This behavior was observed with Steam Big Picture rendering incorrect
icon colors.  The fix has been tested on Ubuntu and SteamOS on Haswell.

Signed-off-by: Cody Northrop <cody@lunarg.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83908
Reviewed-by: Neil Roberts <neil@linux.intel.com>
(cherry picked from commit 83e8bb5b1a50c0105b642d559999f07fa64a982f)
Nominated-by: Matt Turner <mattst88@gmail.com>