freedreno: fix problems if no color buf bound

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/a3xx/compiler: trans_cmp() sanity

Thanks to figuring out 32bit float render target, and adding regdump
test in fdre-a3xx, I can more easily play around with instructions to
figure out range of inputs/outputs/etc.  And from this I can conclude
that cmps.f works more like expected and I can do something much more
simple in trans_cmp() (compared to before which was more closely
emulating the instruction sequence of the blob compiler).

And using sel.b32 (binary 0/1) often makes more sense than sel.f32
(+/- float) or sel.u32 (+/- uint) as it can use the output directly
from cmps.f without needing the 'add.s tmp0, tmp0, -1'.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/a3xx/compiler: handle kill properly (new compiler)

Since 'kill' does not produce a result, the new compiler was happily
optimizing them out.  We need to instead track 'kill's similar to
outputs.  But since there is no non-predicated kill instruction,
(and for flattend if/else we do want them to be predicated), we need
to track the topmost branch condition on the stack and use that as src
arg to the kill.  For a kill at the topmost level, we have to generate
an immediate 1.0 to feed into the cmps.f for setting the predicate
register.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/a3xx/compiler: fix RA typo

Was supposed to be a '+', otherwise we end up with a negative offset and
choosing registers below the assigned range.

This seems to fix the scheduling mystery "solved" by adding in extra
delay slots.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/a3xx/compiler: use (ss) for WAR hazards

Seems texture sample instructions don't immediately consume there
src(s).  In fact, some shaders from blob compiler seem to indiciate that
it does not even count the texture sample instructions when calculating
number of delay slots to fill for non-sample instructions.  (Although so
far it seems inconclusive as to whether this is required.)

In particular, when a src register of a previous texture sample
instruction is clobbered, the (ss) bit is needed to synchronize with the
tex pipeline to ensure it has picked up the previous values before they
are overwritten.

Signed-off-by: Rob Clark <robclark@freedesktop.org>