m100: Revised PL and FSBL prebuilts:

- system_0x3425ef27.bit reverts pin assignments from Ethernet testing
- zynq_fsbl-20140331.1.elf revises FPGA clocks:
  - CLK0: 100MHz
  - CLK1: 200MHz
  - CLK2: 200MHz
  - CLK3:  48MHz