mdss: dsi: Add support to partial update

Add support to send DCS commands to set the partial update region
of interest(ROI) size. These commands will set the column/row start and end
coordinates based on the ROI size.

Change-Id: I1b5944ca057bb082caa70b8c2ad39e11fe418756
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Fix mdss_dsi_cmd_mdp_busy timeout error

Make MDSS clock ON before sending DCS command  to fix
mdss_dsi_cmd_mdp_busy timeout error.

Change-Id: I78a5931715f7a8803af77cd43c6191c225bcecd8
Signed-off-by: Pawan Kumar <pavaku@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: push wait for fences and ping pong done as late as possible

All the configuration up until MDP flush is double buffered. This means
we are able to do all hardware programming without settings taking
effect until flush happens. Perform all programming, wait for fences
and wait for previous frame is done just before the flush in order to
reduce the time between last frame done and kickoff of next one.

Change-Id: I1fd0c7a65309a3b148c8efef61819bfe9a248f29
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: keep clocks on during kickoff operation

There is deadlock scenario where work thread to turn clocks off is
trying to acquire DSI's mdp_busy lock while holding clk_mtx to turn
mdp clocks on.  Meanwhile kickoff thread holds mdp_busy lock and
trying to acquire clk_mtx to turn on clock.
This patch ensure that clocks are kept on and work thread is not
scheduled while kickoff is in progress so that deadlock will not happen.

Change-Id: Iceb5db431a7f9f0e1f56a0e3c1ced2d08d762b86
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Nirmal Abraham <nabrah@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: hotplug: Add io_is_busy interface

Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: dsi-1 as master clock controller at split display case

During split display case, both dsi controllers share the same
dsi pll(dsi0) dsi-0 clock need to be enabled before dsi-1 and disabled
in the reverse order. This mechanism helps using a unified clock control
logic.

Change-Id: I9fe0095b0427c9c2b7fd84c3179bc8364049cce4
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Add support for ULPS mode for DSI

For smart panels that can refresh display from their internal
RAMs, it is possible to configure the DSI clock and data lanes
in Ultra Low Power State (ULPS) during idle static screen
usecase. Add support for this feature.

[myfluxi: Adapt to hammerhead]

Change-Id: I4e94d6a0201262f0675322efc9e39dd93c86edda
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
arm/dt: hammerhead: Enable ULPS mode

Signed-off-by: Dan Trifan <jimsth@gmail.com>