You can move to/from the AVX-512 execution mask registers with KMOVW, so they can be represented as a generic vector of bools, and the backend can do register allocation and instruction selection normally.

That's just like integer/floating-point vectors, where you wouldn't specify if a ```simd![i32, 2]``` should be put in an MMX register, an SSE register or an AVX register, but the backend decides depending on compiler flags.

It's possible that LLVM may want to add or modify instructions so that masked operations are expressed concisely, though.