Add EOR Register support
Add LSL Register support
Add LSL Register test for shift of 256

The contents of the Rm register used for the shift amount is treated as
8-bit so 256 should be treated like 0.
Add LSR Register support

I also found and fixed a bug in Shift_C which was always setting
carryOut to 0 when shift amount was 0.  It is supposed to be
unchanged in this situation.  I had to fix some existing tests after
making this fix since they incorrectly expected the old behaviour.
Fix carry handling for EOR and AND instructions.

I had incorrectly assumed that these two instructions would always
clear the carry flag but it turns out that the call to Shift_C with an
amount of 0 would set carryOut to match the current value of APSR_C.
This means that the state of APSR_C is maintained by these two
instructions.