Emit the correct MUL constant widths

It turns out the MUL width inference rules are different than I
thought.  If we have "A <- B + C", we need the width of A to be the
sum of the widths of B and C -- I thought it was that B and C had the
same width and A was double their width.

This adds some extra logic to make export constants of the correct
width to Flo files.  Like before, it's a bit of a mess and fails when
there's two constants, but I think it's good enough for now...
Fix VCD dumps

WIRE__prev was not getting set during the first cycle's VCD dump,
which can result in inconsistent VCD dumps.  Essentially the idea is
that if your circuit has a wire that starts as non-zero and becomes
zero after the first cycle, the VCD dump will never reflect this
change.
Merge pull request #188 from palmer-dabbelt/master

Fix build related to emitTempNodes
revive Verilog genHarness
merge master
allow testers only for CppBackend
not allow testers for VerilogBackend
testers are called with --test
Make interface to PopCount more generic
Merge pull request #185 from palmer-dabbelt/fix_vcd

Fix VCD dumps
Merge pull request #184 from palmer-dabbelt/mul_const_width

Emit the correct MUL constant widths
Added use of multiword expansion tools to flo backend.
More fixed point features (- on SFix, QR constructors, sample code)
Update NameSuite expected test results
commit c2cd5e886f41171e835a7b563d04b1bf981b716a updated the output
produced by dumpVCDInit(). Update the expected results appropriately.
change over to dims instead of num-cols,num-rows
merge