FogBugz #208110: Fix the L4 clock calculation algorithm

To fix the L4 clock calculation algorithm as the L4 divider
in value of power of 2 instead divisor itself.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #208554: RAM boot to reset Clock Manager during CSEL  0

To enable RAM boot when CSEL = 0. The RAM boot code will put
Main PLL and Peripheral to bypass mode. It will set the QSPI
and NANDSDMMC clock dividers for both PLLs to default value.
Later, the code will disable the RAM boot before triggering
warm reset. The RAM boot code is located at the last 4kB of
on-chip RAM. The purpose of this RAM boot is to overcome boot
up hang issue which due to faulty PLL.

Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v2
- Auto calculate the function size when copying the function