sunxi: dram: Support more DRAM clock speeds (396, 468, 496, 512, 540)

These are some additional interesting DRAM clock frequencies. And
they can be supported, while keeping the PLL5P clock speed at least
not higher than the DRAM clock speed. PLL5P output is used to
clock a lot of peripherals, so we need to be careful not to
break them (or more like some buggy code in the sunxi-3.4
kernel, which just sets hardcoded divisors in some places).

Having 396MHz is nice. It can be used with the tight DDR3-800
timings (CL-tRCD-tRP-tRAS). For comparison, moving to 408MHz
requires extra cycles for many of these timing parameters,
which results in a latency increase.

Having 512MHz and 540MHz is also useful, because they provide better
granularity of the DRAM clock frequency selection around DDR3-1066
speed. And this is an interesting DRAM overclocking target.

The extra five branches add ~120 bytes of code if compiled
for ARM and ~90 bytes of code if compiled for Thumb2.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: dram: Fix dram_tpr3 handling for sun4i

This ifdef wrapped code apparently was introduced as a unification
of sun4i/sun5i and sun7i codebases and assumed that the non-sun7i
part of it was correct. However experiments show that this 4-bit
bitfield behaves in the same way at least on sun4i and sun7i.

Also see the definition in 'include/synopsys/dwcddr21mctl.h':
    #define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14)

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Fix sun6i PLL6 settings

On sun6i the N factor is 1-32, not the 0-31 it is with sun4i / sun5i / sun7i.

Reported-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Fix macro names for mmc and uart reset offsets

Also rewrite sunxi_mmc clock gate/reset enabling code using
setbits_le32.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Allow specifying module in prcm apb0 init function

The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Add basic A23 support

The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Add support for using R_UART as console

The R_UART is the only uart other than UART0 on port F which has
usable pads for attaching a console. Support it so we can still
have a console when using MMC on port F.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Add A23 based tablet Ippo-q8h

The Ippo-q8h is the first A23 based device spotted in the wild.
This was used to bring basic support to u-boot. Add build options
for it

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>