Audit RTCPRE Shift and Mask Values

L0 - RTC Prescaler appears in RCC_CR, bit 20, 2 bits wide (RM0367 Rev 2)
L1 - RTC Prescaler appears in RCC_CR, bit 29, 2 bits wide (RM0038 Rev 10)
F0 - no prescaler setting (RM0091 Rev 7)
F1 - no prescaler setting (RM0041 Rev 4)
F2 - RTC Prescaler appears at RCC_CFGR, bit 16, 4 bits wide (RM0033 Rev 6)
F3 - no prescaler setting (RM0316 Rev 3)
F4 - RTC Prescaler appears at RCC_CFGR, bit 16, 4 bits wide (RM0090 Rev 8)
You are correct, my mistake. Will fix it.


On Sun, Dec 14, 2014 at 4:22 PM, Karl Palsson <notifications@github.com>
wrote:
>
> In include/libopencm3/stm32/f2/rcc.h
> <https://github.com/libopencm3/libopencm3/pull/383#discussion-diff-21801291>
> :
>
> > @@ -136,7 +136,8 @@
> >  #define RCC_CFGR_MCO1_PLL			0x3
> >
> >  /* RTCPRE: HSE division factor for RTC clock */
> > -#define RCC_CFGR_RTCPRE_SHIFT			21
> > +#define RCC_CFGR_RTCPRE_SHIFT			16
> > +#define RCC_CFGR_RTCPRE_MASK			0xf
>
> RM0033r5 implies the mask should be 0x1f. (not sure that's the latest, but
> what ref man were you getting this from? (The 16 is definitely correct)
>
> —
> Reply to this email directly or view it on GitHub
> <https://github.com/libopencm3/libopencm3/pull/383/files#r21801291>.
>