Merge branches/gcc-4_9-branch rev 211054

git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211495 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209457.
       2014-04-16  Andrew  Pinski  <apinski@cavium.com>

       * config/host-linux.c (TRY_EMPTY_VM_SPACE): Change aarch64 ilp32
       definition.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211496 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209419.
       2014-04-15  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

       PR rtl-optimization/60663
       * config/arm/arm.c (arm_new_rtx_costs): Improve ASM_OPERANDS case,
       avoid 0 cost.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211497 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209559.
       2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>

       * config/aarch64/aarch64-builtins.c (BUILTIN_VDQF_DF): Macro
       added.
       * config/aarch64/aarch64-simd-builtins.def (frintn): Use added
       macro.
       * config/aarch64/aarch64-simd.md (<frint_pattern>): Comment
       corrected.
       * config/aarch64/aarch64.md (<frint_pattern>): Likewise.
       * config/aarch64/arm_neon.h (vrnd_f64): Added.
       (vrnda_f64): Likewise.
       (vrndi_f64): Likewise.
       (vrndm_f64): Likewise.
       (vrndn_f64): Likewise.
       (vrndp_f64): Likewise.
       (vrndx_f64): Likewise.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211498 138bc75d-0d04-0410-961f-82ee72b054a4
Add missing testcase in previous backport.

gcc/testsuite/
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209559.
       2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>

       * gcc.target/aarch64/vrnd_f64_1.c : New file.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211504 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209561.
       2014-04-22  Ian Bolton  <ian.bolton@arm.com>

       * config/arm/arm-protos.h (tune_params): New struct members.
       * config/arm/arm.c: Initialise tune_params per processor.
       (thumb2_reorg): Suppress conversion from t32 to t16 when optimizing
       for speed, based on new tune_params.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211505 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209613.
       2014-04-22  Ian Bolton  <ian.bolton@arm.com>

       * config/arm/thumb2.md (*iordi_notdi_di): New pattern.
       (*iordi_notzesidi_di): Likewise.
       (*iordi_notsesidi_di): Likewise.

gcc/testsuite/
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209613.
       2014-04-22  Ian Bolton  <ian.bolton@arm.com>

       * gcc.target/arm/iordi_notdi-1.c: New test.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211506 138bc75d-0d04-0410-961f-82ee72b054a4
Backport from trunk r209614 (stacked on r209613).

gcc/
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209614.
       2014-04-22  Ian Bolton  <ian.bolton@arm.com>

       * config/arm/arm.md (*anddi_notdi_zesidi): New pattern.
       * config/arm/thumb2.md (*iordi_notdi_zesidi): New pattern.

gcc/testsuite/
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209614.
       2014-04-22  Ian Bolton  <ian.bolton@arm.com>

       * gcc.target/arm/anddi_notdi-1.c: New test.
       * gcc.target/arm/iordi_notdi-1.c: New test case.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211507 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209615.
       2014-04-22  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

       * config/arm/arm.c (arm_hard_regno_mode_ok): Loosen
       restrictions on core registers for DImode values in Thumb2.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211508 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209617.
       2014-04-22  James Greenhalgh  <james.greenhalgh@arm.com>

       * config/aarch64/aarch64-simd.md
       (aarch64_cm<optab>di): Always split.
       (*aarch64_cm<optab>di): New.
       (aarch64_cmtstdi): Always split.
       (*aarch64_cmtstdi): New.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211509 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209618.
       2014-04-22  Renlin Li  <Renlin.Li@arm.com>

       * config/aarch64/aarch64.c (aarch64_print_operand_address): Adjust
       the output asm format.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211511 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209627, 209636.
       2014-04-22  Renlin  <renlin.li@arm.com>
                   Jiong Wang  <jiong.wang@arm.com>

       * config/aarch64/aarch64.h (aarch64_frame): Delete "fp_lr_offset".
       * config/aarch64/aarch64.c (aarch64_layout_frame)
       (aarch64_initial_elimination_offset): Likewise.

       2014-04-22  Marcus Shawcroft  <marcus.shawcroft@arm.com>

       * config/aarch64/aarch64.c (aarch64_initial_elimination_offset):
       Fix indentation.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211512 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209640.
       2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>

       * gcc/config/aarch64/aarch64-simd.md (aarch64_s<optab><mode>):
       Pattern extended.
       * config/aarch64/aarch64-simd-builtins.def (sqneg): Iterator
       extended.
       (sqabs): Likewise.
       * config/aarch64/arm_neon.h (vqneg_s64): New intrinsic.
       (vqnegd_s64): Likewise.
       (vqabs_s64): Likewise.
       (vqabsd_s64): Likewise.

gcc/testsuite/
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209640.
       2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>

       * gcc.target/aarch64/vqneg_s64_1.c: New testcase.
       * gcc.target/aarch64/vqabs_s64_1.c: New testcase.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211514 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
 
	Backport from trunk r209641, 209642.
	2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>

	* config/aarch64/aarch64-builtins.c (TYPES_REINTERP): Removed.
	(aarch64_types_signed_unsigned_qualifiers): Qualifier added.
	(aarch64_types_signed_poly_qualifiers): Likewise.
	(aarch64_types_unsigned_signed_qualifiers): Likewise.
	(aarch64_types_poly_signed_qualifiers): Likewise.
	(TYPES_REINTERP_SS): Type macro added.
	(TYPES_REINTERP_SU): Likewise.
	(TYPES_REINTERP_SP): Likewise.
	(TYPES_REINTERP_US): Likewise.
	(TYPES_REINTERP_PS): Likewise.
	(aarch64_fold_builtin): New expression folding added.
	* config/aarch64/aarch64-simd-builtins.def (REINTERP):
	Declarations removed.
	(REINTERP_SS): Declarations added.
	(REINTERP_US): Likewise.
	(REINTERP_PS): Likewise.
	(REINTERP_SU): Likewise.
	(REINTERP_SP): Likewise.
	* config/aarch64/arm_neon.h (vreinterpret_p8_f64): Implemented.
	(vreinterpretq_p8_f64): Likewise.
	(vreinterpret_p16_f64): Likewise.
	(vreinterpretq_p16_f64): Likewise.
	(vreinterpret_f32_f64): Likewise.
	(vreinterpretq_f32_f64): Likewise.
	(vreinterpret_f64_f32): Likewise.
	(vreinterpret_f64_p8): Likewise.
	(vreinterpret_f64_p16): Likewise.
	(vreinterpret_f64_s8): Likewise.
	(vreinterpret_f64_s16): Likewise.
	(vreinterpret_f64_s32): Likewise.
	(vreinterpret_f64_s64): Likewise.
	(vreinterpret_f64_u8): Likewise.
	(vreinterpret_f64_u16): Likewise.
	(vreinterpret_f64_u32): Likewise.
	(vreinterpret_f64_u64): Likewise.
	(vreinterpretq_f64_f32): Likewise.
	(vreinterpretq_f64_p8): Likewise.
	(vreinterpretq_f64_p16): Likewise.
	(vreinterpretq_f64_s8): Likewise.
	(vreinterpretq_f64_s16): Likewise.
	(vreinterpretq_f64_s32): Likewise.
	(vreinterpretq_f64_s64): Likewise.
	(vreinterpretq_f64_u8): Likewise.
	(vreinterpretq_f64_u16): Likewise.
	(vreinterpretq_f64_u32): Likewise.
	(vreinterpretq_f64_u64): Likewise.
	(vreinterpret_s64_f64): Likewise.
	(vreinterpretq_s64_f64): Likewise.
	(vreinterpret_u64_f64): Likewise.
	(vreinterpretq_u64_f64): Likewise.
	(vreinterpret_s8_f64): Likewise.
	(vreinterpretq_s8_f64): Likewise.
	(vreinterpret_s16_f64): Likewise.
	(vreinterpretq_s16_f64): Likewise.
	(vreinterpret_s32_f64): Likewise.
	(vreinterpretq_s32_f64): Likewise.
	(vreinterpret_u8_f64): Likewise.
	(vreinterpretq_u8_f64): Likewise.
	(vreinterpret_u16_f64): Likewise.
	(vreinterpretq_u16_f64): Likewise.
	(vreinterpret_u32_f64): Likewise.
	(vreinterpretq_u32_f64): Likewise.

	2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>

	* config/aarch64/aarch64/aarch64-builtins.c (TYPES_REINTERP): Removed.
	* config/aarch64/aarch64/aarch64-simd-builtins.def (REINTERP): Removed.
	(vreinterpret_p8_s8): Likewise.
	* config/aarch64/aarch64/arm_neon.h (vreinterpret_p8_s8): Uses cast.
	(vreinterpret_p8_s16): Likewise.
	(vreinterpret_p8_s32): Likewise.
	(vreinterpret_p8_s64): Likewise.
	(vreinterpret_p8_f32): Likewise.
	(vreinterpret_p8_u8): Likewise.
	(vreinterpret_p8_u16): Likewise.
	(vreinterpret_p8_u32): Likewise.
	(vreinterpret_p8_u64): Likewise.
	(vreinterpret_p8_p16): Likewise.
	(vreinterpretq_p8_s8): Likewise.
	(vreinterpretq_p8_s16): Likewise.
	(vreinterpretq_p8_s32): Likewise.
	(vreinterpretq_p8_s64): Likewise.
	(vreinterpretq_p8_f32): Likewise.
	(vreinterpretq_p8_u8): Likewise.
	(vreinterpretq_p8_u16): Likewise.
	(vreinterpretq_p8_u32): Likewise.
	(vreinterpretq_p8_u64): Likewise.
	(vreinterpretq_p8_p16): Likewise.
	(vreinterpret_p16_s8): Likewise.
	(vreinterpret_p16_s16): Likewise.
	(vreinterpret_p16_s32): Likewise.
	(vreinterpret_p16_s64): Likewise.
	(vreinterpret_p16_f32): Likewise.
	(vreinterpret_p16_u8): Likewise.
	(vreinterpret_p16_u16): Likewise.
	(vreinterpret_p16_u32): Likewise.
	(vreinterpret_p16_u64): Likewise.
	(vreinterpret_p16_p8): Likewise.
	(vreinterpretq_p16_s8): Likewise.
	(vreinterpretq_p16_s16): Likewise.
	(vreinterpretq_p16_s32): Likewise.
	(vreinterpretq_p16_s64): Likewise.
	(vreinterpretq_p16_f32): Likewise.
	(vreinterpretq_p16_u8): Likewise.
	(vreinterpretq_p16_u16): Likewise.
	(vreinterpretq_p16_u32): Likewise.
	(vreinterpretq_p16_u64): Likewise.
	(vreinterpretq_p16_p8): Likewise.
	(vreinterpret_f32_s8): Likewise.
	(vreinterpret_f32_s16): Likewise.
	(vreinterpret_f32_s32): Likewise.
	(vreinterpret_f32_s64): Likewise.
	(vreinterpret_f32_u8): Likewise.
	(vreinterpret_f32_u16): Likewise.
	(vreinterpret_f32_u32): Likewise.
	(vreinterpret_f32_u64): Likewise.
	(vreinterpret_f32_p8): Likewise.
	(vreinterpret_f32_p16): Likewise.
	(vreinterpretq_f32_s8): Likewise.
	(vreinterpretq_f32_s16): Likewise.
	(vreinterpretq_f32_s32): Likewise.
	(vreinterpretq_f32_s64): Likewise.
	(vreinterpretq_f32_u8): Likewise.
	(vreinterpretq_f32_u16): Likewise.
	(vreinterpretq_f32_u32): Likewise.
	(vreinterpretq_f32_u64): Likewise.
	(vreinterpretq_f32_p8): Likewise.
	(vreinterpretq_f32_p16): Likewise.
	(vreinterpret_s64_s8): Likewise.
	(vreinterpret_s64_s16): Likewise.
	(vreinterpret_s64_s32): Likewise.
	(vreinterpret_s64_f32): Likewise.
	(vreinterpret_s64_u8): Likewise.
	(vreinterpret_s64_u16): Likewise.
	(vreinterpret_s64_u32): Likewise.
	(vreinterpret_s64_u64): Likewise.
	(vreinterpret_s64_p8): Likewise.
	(vreinterpret_s64_p16): Likewise.
	(vreinterpretq_s64_s8): Likewise.
	(vreinterpretq_s64_s16): Likewise.
	(vreinterpretq_s64_s32): Likewise.
	(vreinterpretq_s64_f32): Likewise.
	(vreinterpretq_s64_u8): Likewise.
	(vreinterpretq_s64_u16): Likewise.
	(vreinterpretq_s64_u32): Likewise.
	(vreinterpretq_s64_u64): Likewise.
	(vreinterpretq_s64_p8): Likewise.
	(vreinterpretq_s64_p16): Likewise.
	(vreinterpret_u64_s8): Likewise.
	(vreinterpret_u64_s16): Likewise.
	(vreinterpret_u64_s32): Likewise.
	(vreinterpret_u64_s64): Likewise.
	(vreinterpret_u64_f32): Likewise.
	(vreinterpret_u64_u8): Likewise.
	(vreinterpret_u64_u16): Likewise.
	(vreinterpret_u64_u32): Likewise.
	(vreinterpret_u64_p8): Likewise.
	(vreinterpret_u64_p16): Likewise.
	(vreinterpretq_u64_s8): Likewise.
	(vreinterpretq_u64_s16): Likewise.
	(vreinterpretq_u64_s32): Likewise.
	(vreinterpretq_u64_s64): Likewise.
	(vreinterpretq_u64_f32): Likewise.
	(vreinterpretq_u64_u8): Likewise.
	(vreinterpretq_u64_u16): Likewise.
	(vreinterpretq_u64_u32): Likewise.
	(vreinterpretq_u64_p8): Likewise.
	(vreinterpretq_u64_p16): Likewise.
	(vreinterpret_s8_s16): Likewise.
	(vreinterpret_s8_s32): Likewise.
	(vreinterpret_s8_s64): Likewise.
	(vreinterpret_s8_f32): Likewise.
	(vreinterpret_s8_u8): Likewise.
	(vreinterpret_s8_u16): Likewise.
	(vreinterpret_s8_u32): Likewise.
	(vreinterpret_s8_u64): Likewise.
	(vreinterpret_s8_p8): Likewise.
	(vreinterpret_s8_p16): Likewise.
	(vreinterpretq_s8_s16): Likewise.
	(vreinterpretq_s8_s32): Likewise.
	(vreinterpretq_s8_s64): Likewise.
	(vreinterpretq_s8_f32): Likewise.
	(vreinterpretq_s8_u8): Likewise.
	(vreinterpretq_s8_u16): Likewise.
	(vreinterpretq_s8_u32): Likewise.
	(vreinterpretq_s8_u64): Likewise.
	(vreinterpretq_s8_p8): Likewise.
	(vreinterpretq_s8_p16): Likewise.
	(vreinterpret_s16_s8): Likewise.
	(vreinterpret_s16_s32): Likewise.
	(vreinterpret_s16_s64): Likewise.
	(vreinterpret_s16_f32): Likewise.
	(vreinterpret_s16_u8): Likewise.
	(vreinterpret_s16_u16): Likewise.
	(vreinterpret_s16_u32): Likewise.
	(vreinterpret_s16_u64): Likewise.
	(vreinterpret_s16_p8): Likewise.
	(vreinterpret_s16_p16): Likewise.
	(vreinterpretq_s16_s8): Likewise.
	(vreinterpretq_s16_s32): Likewise.
	(vreinterpretq_s16_s64): Likewise.
	(vreinterpretq_s16_f32): Likewise.
	(vreinterpretq_s16_u8): Likewise.
	(vreinterpretq_s16_u16): Likewise.
	(vreinterpretq_s16_u32): Likewise.
	(vreinterpretq_s16_u64): Likewise.
	(vreinterpretq_s16_p8): Likewise.
	(vreinterpretq_s16_p16): Likewise.
	(vreinterpret_s32_s8): Likewise.
	(vreinterpret_s32_s16): Likewise.
	(vreinterpret_s32_s64): Likewise.
	(vreinterpret_s32_f32): Likewise.
	(vreinterpret_s32_u8): Likewise.
	(vreinterpret_s32_u16): Likewise.
	(vreinterpret_s32_u32): Likewise.
	(vreinterpret_s32_u64): Likewise.
	(vreinterpret_s32_p8): Likewise.
	(vreinterpret_s32_p16): Likewise.
	(vreinterpretq_s32_s8): Likewise.
	(vreinterpretq_s32_s16): Likewise.
	(vreinterpretq_s32_s64): Likewise.
	(vreinterpretq_s32_f32): Likewise.
	(vreinterpretq_s32_u8): Likewise.
	(vreinterpretq_s32_u16): Likewise.
	(vreinterpretq_s32_u32): Likewise.
	(vreinterpretq_s32_u64): Likewise.
	(vreinterpretq_s32_p8): Likewise.
	(vreinterpretq_s32_p16): Likewise.
	(vreinterpret_u8_s8): Likewise.
	(vreinterpret_u8_s16): Likewise.
	(vreinterpret_u8_s32): Likewise.
	(vreinterpret_u8_s64): Likewise.
	(vreinterpret_u8_f32): Likewise.
	(vreinterpret_u8_u16): Likewise.
	(vreinterpret_u8_u32): Likewise.
	(vreinterpret_u8_u64): Likewise.
	(vreinterpret_u8_p8): Likewise.
	(vreinterpret_u8_p16): Likewise.
	(vreinterpretq_u8_s8): Likewise.
	(vreinterpretq_u8_s16): Likewise.
	(vreinterpretq_u8_s32): Likewise.
	(vreinterpretq_u8_s64): Likewise.
	(vreinterpretq_u8_f32): Likewise.
	(vreinterpretq_u8_u16): Likewise.
	(vreinterpretq_u8_u32): Likewise.
	(vreinterpretq_u8_u64): Likewise.
	(vreinterpretq_u8_p8): Likewise.
	(vreinterpretq_u8_p16): Likewise.
	(vreinterpret_u16_s8): Likewise.
	(vreinterpret_u16_s16): Likewise.
	(vreinterpret_u16_s32): Likewise.
	(vreinterpret_u16_s64): Likewise.
	(vreinterpret_u16_f32): Likewise.
	(vreinterpret_u16_u8): Likewise.
	(vreinterpret_u16_u32): Likewise.
	(vreinterpret_u16_u64): Likewise.
	(vreinterpret_u16_p8): Likewise.
	(vreinterpret_u16_p16): Likewise.
	(vreinterpretq_u16_s8): Likewise.
	(vreinterpretq_u16_s16): Likewise.
	(vreinterpretq_u16_s32): Likewise.
	(vreinterpretq_u16_s64): Likewise.
	(vreinterpretq_u16_f32): Likewise.
	(vreinterpretq_u16_u8): Likewise.
	(vreinterpretq_u16_u32): Likewise.
	(vreinterpretq_u16_u64): Likewise.
	(vreinterpretq_u16_p8): Likewise.
	(vreinterpretq_u16_p16): Likewise.
	(vreinterpret_u32_s8): Likewise.
	(vreinterpret_u32_s16): Likewise.
	(vreinterpret_u32_s32): Likewise.
	(vreinterpret_u32_s64): Likewise.
	(vreinterpret_u32_f32): Likewise.
	(vreinterpret_u32_u8): Likewise.
	(vreinterpret_u32_u16): Likewise.
	(vreinterpret_u32_u64): Likewise.
	(vreinterpret_u32_p8): Likewise.
	(vreinterpret_u32_p16): Likewise.
	(vreinterpretq_u32_s8): Likewise.
	(vreinterpretq_u32_s16): Likewise.
	(vreinterpretq_u32_s32): Likewise.
	(vreinterpretq_u32_s64): Likewise.
	(vreinterpretq_u32_f32): Likewise.
	(vreinterpretq_u32_u8): Likewise.
	(vreinterpretq_u32_u16): Likewise.
	(vreinterpretq_u32_u64): Likewise.
	(vreinterpretq_u32_p8): Likewise.
	(vreinterpretq_u32_p16): Likewise.

gcc/testsuite
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
 
	Backport from trunk r209642.
	2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>

	* gcc.target/aarch64/vreinterpret_f64_1.c: New.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211515 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209643.
       2014-04-22  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

       * config/aarch64/aarch64.c (TARGET_FLAGS_REGNUM): Define.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211516 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209645.
       2014-04-22  Andrew Pinski  <apinski@cavium.com>

       * config/aarch64/aarch64.c (aarch64_load_symref_appropriately):
       Handle TLS for ILP32.
       * config/aarch64/aarch64.md (tlsie_small): Rename to ...
       (tlsie_small_<mode>): this and handle PTR.
       (tlsie_small_sidi): New pattern.
       (tlsle_small): Change to an expand to handle ILP32.
       (tlsle_small_<mode>): New pattern.
       (tlsdesc_small): Rename to ...
       (tlsdesc_small_<mode>): this and handle PTR.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211517 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209649.
       2014-04-22  Yufeng Zhang  <yufeng.zhang@arm.com>

       * longlong.h: Merge from glibc.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211518 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209659.
       2014-04-22  Richard Henderson  <rth@redhat.com>

       * config/aarch64/aarch64 (addti3, subti3): New expanders.
       (add<GPI>3_compare0): Remove leading * from name.
       (add<GPI>3_carryin): Likewise.
       (sub<GPI>3_compare0): Likewise.
       (sub<GPI>3_carryin): Likewise.
       (<su_optab>mulditi3): New expander.
       (multi3): New expander.
       (madd<GPI>): Remove leading * from name.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211519 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r209701, 209702, 209703, 209704, 209705.
	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (arm_rev16si2): New pattern.
	(arm_rev16si2_alt): Likewise.
	* config/arm/arm.c (arm_new_rtx_costs): Handle rev16 case.

	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
	* config/aarch64/aarch64.md (rev16<mode>2): New pattern.
	(rev16<mode>2_alt): Likewise.
	* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle rev16 case.
	* config/arm/aarch-common.c (aarch_rev16_shright_mask_imm_p): New.
	(aarch_rev16_shleft_mask_imm_p): Likewise.
	(aarch_rev16_p_1): Likewise.
	(aarch_rev16_p): Likewise.
	* config/arm/aarch-common-protos.h (aarch_rev16_p): Declare extern.
	(aarch_rev16_shright_mask_imm_p): Likewise.
	(aarch_rev16_shleft_mask_imm_p): Likewise.

	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/aarch-common-protos.h (alu_cost_table): Add rev field.
	* config/arm/aarch-cost-tables.h (generic_extra_costs): Specify
	rev cost.
	(cortex_a53_extra_costs): Likewise.
	(cortex_a57_extra_costs): Likewise.
	* config/arm/arm.c (cortexa9_extra_costs): Likewise.
	(cortexa7_extra_costs): Likewise.
	(cortexa8_extra_costs): Likewise.
	(cortexa12_extra_costs): Likewise.
	(cortexa15_extra_costs): Likewise.
	(v7m_extra_costs): Likewise.
	(arm_new_rtx_costs): Handle BSWAP.

	2013-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.c (cortexa8_extra_costs): New table.
	(arm_cortex_a8_tune): New tuning struct.
	* config/arm/arm-cores.def (cortex-a8): Use cortex_a8 tuning struct.

	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.c (arm_new_rtx_costs): Handle FMA.

gcc/testsuite/
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r209704, 209705.
	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* gcc.target/arm/rev16.c: New test.

	2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* gcc.target/aarch64/rev16_1.c: New test.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211520 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-23  Yvan Roux  <yvan.roux@linaro.org>

       Backport from trunk r209706.
       2014-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

       * config/aarch64/aarch64.c (aarch64_rtx_costs): Handle BSWAP.



git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211521 138bc75d-0d04-0410-961f-82ee72b054a4