First contribution : Vhdl_reader is able to get the entity name
Added:
Entity class
Wire class

Renamed:
Entity directory --> vhdl_objects
Added:
Class Library

Work:
trying to reproduce the "contains" property
pdfWriter imporve
AutoTune width and height
Inouts added (margin, ...)
Outs addes (side)
Added :
Multi wire representation (in , inouts, out)
Added : multiwire (out)
factorisation :
wire direction is determine by adding category (add_input, ...)
Modify line width for wires
Magic number hunt
Entity and Libs are extracted from file
Big improvement.
take a real VHDL file int a schematic!

Need to improve boundary recognitions for std_logic_vector
Dependency reorganisation
remore french accent
Big improvements in special bus size handling
Merge branch 'master' of gitlab.fyrdun.eu:LaurentCabaret/pyvhdl2sch
Arg are intruduced
pyV2S.py is now executable
Add a demo mode :
if no vhdl file is given the demo one is used
datas/test_files/demo.vhd
Program can now take multiple files as arguments
cleaning