arc: [trivial] Fix typo with invalid memory address format in log

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: Add a simple test for STAR 9000830091

Since that is the first such test, also add a basic infrastructure for test
suite and README entry.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: Always read BCRs when examining the target

Yet, configure optional registers only when compatibility mode is not
enabled.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: Detect CCMs based on BCRs

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: Add an artificial delay when reading from DDR memory

When reading more than one word subsequently from DDR memory there was a problem that
second and further words were read as 0, instead of a real content. That
could have been easily reproduced with:

mww 0x10000000 0xde
mww 0x10000004 0xad
mdw 0x10000004 1
mdw 0x10000000 2

For the second read we would get "0x000000de 0x00000000". One way to fix
that is to reduce JTAG frequency. For example with EM Starter Kit EM7D@30MHz
error was resolved with JTAG frequency 2.2MHz. That increased time of bulk
memory reads (100 000 consecutive 32bit words) in 3.1 times plus it affects
all of the other JTAG operations.  Another solution (implemented in this
patch) is to write address of a memory word to read each time before reading
it. In general that is unnecessary for consecutive reads, since address is
auto-incremented, so here it is just an artificial way to add a required
delay. In comparison to reduced JTAG speed this patch decreases performance
of the same bulk memory read in 2.7 times, and it affects only memory reads
- all other JTAG operations are done at the same pace as before. In addition
using functionality added in previous patches memory layer applies this
delay only to the non-CCM memories, so ICCM/DCCM are not affected by this
patch as well.

I do have a feeling that this might be a bug in EM7D JTAG interface, but I
don't really know. See Synopsys STARs 9000830091 and 9000832538 for details.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: Workaround a possible issue with reading DDR memory

Similar to previous STAR, sometimes we read 0 instead of real memory
content, only this time it is a first read from memory, so we cannot add
artificial address writes. Instead now OpenOCD will check for JTAG status
register and will spin on this until it will set RD (ready) bit. In practice
it almost always set and I've never seen it not being set _before_ doing
memory read. So that is kind of a dummy useless check, since I haven't seen
cases where we would have to really wait for the JTAG interface. That
however seems to resolve the problem with failed reads, perhaps by adding a
delay between cache flush and memory read. Though that is quite strange
since in terms of the core time, there is already significant time between
flush and read.

Like with extra address writes this is applied only to "slow" memory (DDR)
and not to CCMs. It is also applied only to memory reads, though in theory
we should do this before each operations, that would add additional
performance penalty, and I don't feel inclined to decrease performance until
it will be obvious that it is required.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: Add an option to enable paranoia checks for JTAG status RD

Add an option "arc jtag always-check-status-rd on|off" that will force ARC
JTAG layer to check for RD bit of JTAG Status register. See already
existing code that does this before reading from DDR memory. This option is
off by default, since there are no known cases where this check is required
for anything else other than read from DDR memory.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: [trivial] Formatting of AUX register values in log

Use %08x instead of %x, so that presentation will be same as for core
registers

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: Add a warning when SW breakpoint has been overwritten externally

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: Add JTAG STATUS.FL checks after each operation

Check for FL bit in JTAG STATUS register and return error if this bit is
set, which usually indicates some kind of an error.

This however is disabled by default because it is known to break JTAG: there
is an undesired extra write after the indented one, so if we write, say,
DEBUG AUX register at 0x5, then we will also write same value to PC register
at 0x6, which is totally undesired.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>