or1k-elf-loader: make it compatible with C++

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
system: de1: add post build script

This is an example of post build script. It extracts and displays
fitting summary and Fmax for the design.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
system: de1: set script file attibute to 'x'

ORPSoC now starts shell scripts without invoquing bash
(see commit 76dcafe76c92). So turn the script to an
executable.

Fix white spaces at the same time.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Do not print file names for grep command
Rename or1k-elf-loader to elf-loader

There's nothing or1k specific to this 'core' anymore, so let's
use a more common name for it.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Remove generic system

The generic system has been broken for a long time and only adds
confusion. It has been more or less replaced with or1200-generic
elf-loader: add missing headers in vpi_wrapper.c

No error while using Icarus but Modelsim complains.

Add missing stdlib.h and ctype.h required for NULL, free() and
isspace().

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
or1200-generic: verilator: add top_module param

In section verilator top_module in now mandatory for the
simulated system/core.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
or1200-generic: Regenerate wb_intercon

wb_intercon_gen now adds a wb_data_resize block for 8 bit slaves
Note though that this isn't completely automatic, so port width has
to be changed manually in the generated RTL
wb_intercon: Small wb_intercon_gen fixes
or1200-generic: update verilator support

This patch removes the local copy of elf-loader in or1200-generic.
This copy is no longer needed because fusesoc now adds verilator
files from all cores.

The verilator testbench is also cleaned-up and adapted to the
up-to-date elf-loader.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
cores: add verilog_utils core

The idea behind the verilog_utils core is to gather convinience
functions in one place, that other cores can pull in and use.
As a start, it contains an implementation of clog2, for
tools that doesn't yet have proper support for $clog2
(most notable ISE < 14.1).
Also functions for find first/last one are included.
wb_intercon: use verilog_utils

Takes the recently added verilog_utils into use,
which make the implementation slightly cleaner.
By this, a bug in the $clog2 implementation in ISE < 14.1
is resolved.
And a workaround for a bug in verilator is removed
(more recent version of verilator than where the bug was
present, is needed for other reasons anyway).
wb_intercon: fix single slave connections

When a master only had a single slave, there would be no
connection made between the master and slave.
The reason was that _gen_mux was never called on
master.slaves == 1, even though _gen_mux has code to handle
the condition.
A note on that though, a wb_mux will still be instantiated,
but this is IMO correct behaviour instead of hard connect the
wires between the master and the slave, since additional
address matching logic will be added with wb_mux.
add verilator_tb_utils core

The verilator_tb_utils core consist of the non-or1200 specific
part of the or1200-generic verilator test bench and
wraps them in a reusable C++ class.

The biggest difference is probably the argument parsing,
the custom strcmp parsing have been replaced with argument
parsing from the argp library.
The argp library has support for parent/child parser,
and the VerilatorTbUtils class parser is intended to be
used as a child parser, i.e. the arguments can be
extended by the main test bench that instantiates the class.
or1200-generic: use verilator_tb_utils

This removes all non-or1200 specific code that is now
implemented in verilator_tb_utils instead.

An (almost) empty argument parser template is added,
which only purpose right now is to initiate the child parser
in verilator_tb_utils.

A signal handler is also added to catch ctrl-c.
Merge branch 'wb_intercon' of github.com:skristiansson/orpsoc-cores into master
Merge branch 'verilog_utils' of github.com:skristiansson/orpsoc-cores into master
wb_intercon: allow single master/slaves

The result of clog2(1) = 0, which will result in
master/slave_sel bit vectors of [-1:0].
Threat the special case of num_masters/slaves == 1,
so a bit vector [0:0] is created.
wb_intercon: fix multiple masters to single slave connections

The commit: 5f7cbf7e77a6d54641efc4c832628265a605d1e2
'wb_intercon: fix single slave connections'
took care of the case with a single master connected to
a single slave. The case with several masters connected
to a single slave was however oversighted.