Fixed check for MDIO header (32 bits high), to ensure correct start sequence.
changes so that andrew can build against work qdr

Plenty of work still to be done on the QDR though

Conflicts resolved by taking theirs

Conflicts:
	xps_base/XPS_ROACH2_base/pcores/opb_qdr_sniffer_v1_00_a/hdl/verilog/opb_qdr_sniffer.v
	xps_base/XPS_ROACH2_base/pcores/qdr_controller_v1_00_a/hdl/verilog/qdrc_phy.v
	xps_base/XPS_ROACH2_base/pcores/qdr_controller_v1_00_a/hdl/verilog/qdrc_phy_bit_correct.v
	xps_base/XPS_ROACH2_base/pcores/qdr_controller_v1_00_a/hdl/verilog/qdrc_phy_bit_train.v
	xps_base/XPS_ROACH2_base/pcores/qdr_controller_v1_00_a/hdl/verilog/qdrc_phy_burst_align.v
	xps_base/XPS_ROACH2_base/pcores/qdr_controller_v1_00_a/hdl/verilog/qdrc_rd.v
	xps_library/@xps_qdr/gen_mhs_ip.m
	xps_library/qdr_mask.m
	xps_library/xps_library.mdl
Removing bw_n signal from the qdr

These signals arent routed in on the ROACH2
Change to improve timing

Changing the edge detect from async to sync to improve timing
Updates to the qdr
the synthesis directives dont support *s
Changes to get QDR3 working
Changes to get QDR3 working

Set up the area constraints for QDR3, to ease timing.

The pins for QDR3 are spread over 3 different banks making it hard to meet
timing at higher frequencies. This also makes it hard to constrain. BlaH!
Fixing sys_clk2x issue

sysc_clk2x was being constrained even when it was optimised away,
this causes errors. sys_clk2x is now only constrained when any
qdr is used.
Setting the read latency statically to 10 cycles

Also adding that latency to the QDR simulation model

Conflicts: took theirs

Conflicts:
	xps_library/xps_library.mdl
Fix KATADC 3-wire chip select for ZDOK1 on ROACH2

The KATADC 3-wire chip select signal for ZDOK1 on ROACH2 had the wrong
polarity.  This commit fixes that problem.
Fix KATADC 3-wire clock for ROACH2 ZDOK1

The KATADC 3-wire clock for ROACH2 ZDOK1 was being driven by the 3-wire clock
for ZDOK0.  This made it impossible to program a KATADC chip in ZDOK1 on
ROACH2.  This commit fixes that particular problem.
Fix OPB clock for three ADC blocks on ROACH2

For some reason, three ADC blocks on ROACH2 had their OPB clock driven by
sys_clk instead of epb_clk.  This restores those blocks to use epb_clk for
their OPB clock source (like every other OPB block in the system).
sysclk_2x calculation fix - integer rounding error
Revert "sysclk_2x calculation fix - integer rounding error"

This reverts commit bc9dae64dcfed91a7446d66f7c38eb6c7931f620.
adding promisc mode to the kat tge core for R2

Setting the promisc mode allows all traffic through to the fabric
except packets destined for the cpu port, use this option if
broadcast traffic is crashing the PPC. It allows the fabric to
see all packets that arrive on the interface.

conflicts: took theirs

Conflicts:
	xps_library/@xps_tengbe_v2/xps_tengbe_v2.m
Use pipeline blocks instead of regular delays...

...inside bitsnap blocks, before the snapshot.

conflicts: took theirs

Conflicts:
	xps_library/tengbe_v2_mask.m
Debug options for 10Gbe yellow block.

Conflicts: Took theirs
	xps_library/tengbe_v2_mask.m
The debug reset line on the 10gbe will only appear if debug counters are present.
Debug options for 10Gbe yellow block.