cappuccino/lsu: perform stores to cache during cache inhibit

To keep the cache memory coherent under the situation
where a system writes to a cache-inhibit memory area
while the dmmu is on, but reads from it when it is off,
writes have to go through to the cache in case of a hit.
cappuccino: move reading of rf port A to decode

The benefit of this is that it makes it possible to add an extra
registering stage between decode and execute, avoiding some
critical paths that comes from adding a lot of logic straight to
the rf RAM outputs.

This also allows for the PIPELINED multiplier to hook up
to the outputs at decode stage, to be able to add an extra
registering stage to the end of that.

The disadvantage is that extra forwarding logic is
needed between decode and execute.
cappuccino/decode: fix PIPELINED multiplier interlocks

ctrl_to_decode interlock needs to cover both port a and b
cappuccino/fetch: latch rf address on bus_access_done

Since the pipeline is advanced on this signal, the register
file gating should follow that.
cappuccino/decode: make branch indicate signal more lightweigth

decode_bubble_o is a very heavy weight signal to depend on,
the only time decode_bubble_o can be asserted when there
is a branch instruction in decode stage is when there is
either an instruction in ctrl/mem stage or execute stage
producing a result that is needed by the branch.

Explicitly use that condition in the branch_to_reg signal.
cappuccino: move overflow disable to execute_alu

This will set the originating signals to zero when
FEATURE_OVERFLOW is "NONE".
make carry flag optional with FEATURE_CARRY_FLAG

The carry flag (SR[CY]) is mandatory by the spec, but
is rarely used by software.
This makes it possible to disable the support for it to
save resources and untangle some potential critical paths.

Currently only cappuccino actually disables the support upon
setting the FEATURE_CARRY_FLAG parameter to "NONE".
cappuccino/lsu: decouple storebuffer from external bus

Instead of exposing the store buffer directly to the external
bus, add an extra registered stage.
This will add a one-cycle latency on the first write when
emptying the store-buffer, but will at the same time
remove critical paths.

This should also make disabling the store buffer all together
more straight forward, but the work to make that possible is not
done here.
Merge branch 'master' of github.com:openrisc/mor1kx into multicore

Conflicts:
	rtl/verilog/mor1kx_lsu_cappuccino.v