Comments and style cleaned up, prebuffer taken out (with proper timing closure, it's unnecessary. If buffers get too large, you can simple wait longer before running the algorithm portion. However, there might be an upper limit on the size of a frame you can test on the Spartan 6 (these should be alleviated when using a larger FPGA like the Virtex 7)). Algorithm pipelining in progress, although I still see no easy way to repipeline things.