Refactoring interface with memaccess + fix bug in sc address comparison
Introducing a helper function for sml to write in memory
Added a 256 bits memory write interface
(Useful for capability memory operations)
Updated  pretty printing for CHERI load instructions
Introducing a per core coherent private dcache L1
Experienced with hash functions for l1 dcache index/tag
Adding a cheri specific memory subsystem
Added cache CHERI hierarchy
Fixed L2 update in CHERI memory + log info
Refining CHERI cache hierarchy and logging info
Fixed CHERI coherence mechanism on L2 evictions
Added short tags check for L1 invalidates
Added privatel1-sharedl2 from cheri to standard build
Updated cheri memory subsystem to be capability aware