MIPS: Added assembler, dissasembler and necessary support for MIPS32r6 support.

TEST=
MIPS: Correct assert check on 21bit offset compact branch.

TEST=
MIPS: Completed MIPS32r6 dissasembler, and updated test-disasm-mips and test-assembler-mips for MIPS32r6 ISA.

TEST=cctests/test-dissasm-mips64,test-assembler-mips
Merge branch 'mips64-R6' of github.com:paul99/v8m-rb into mips64-gbl-r6
MIPS: Refactor heap numbers compare in ICCompare stub for r6.

TEST=
MIPS64: Fix the loongson case for the div instructions.
MIPS32: Added support for the r6 instructions.
Merge branch 'mips64-R6' of github.com:paul99/v8m-rb into mips64-R6
MIPS: Temporary reserve fpu reg for compare operations in fp32 mode.

TEST=
BUG=
MIPS32: Added mul, muh, mod and div (R6 instructions).
MIPS32: Added mulu, muhu, modu and divu (R6 instructions).
MIPS32: Added support to the simulator for the mulu, muhu, modu and divu (R6).
MIPS: Remove merge error in status file.

TEST=
MIPS: Unbreak r6 build and fix bugs.

Number of allocatable general registers matched to number of fpu
alloctable registers.

Disabled JR -> J, JALR -> JAL optimizations.
MIPS: Fix extended Mul() macro for r6.

TEST=mjsunit/smi-mul
Merge branch 'mips64-R6' of github.com:paul99/v8m-rb into mips64-gbl-r6
MIPS: Added missing op codes for new immediate instructions, and relocated CLZ instruction for r6.

TEST=cctests/test-dissasm-mips64