ion: don't use id 0 for handle cookie

ion userspace clients think that the cookie is a pointer, so they
use NULL to check if the handle has been initialized.  Set the first
id number to 1.

Change-Id: Ifb9af6029a8b08f57e41bc6160cc11e11001a2a9
Signed-off-by: Colin Cross <ccross@android.com>
Git-commit: 66df93b4c9e78cf433b76d7fe3da4cc7fd06c36b
Git-repo: https://android.googlesource.com/kernel/common
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
msm: msm-pm: Remove timeout waiting for cpu to power collapse

The delays in the CPU_DYING notication path could result in the core
initiating the hotplug to send out CPU_DEAD notifications after
msm_pm_wait_cpu_shutdown() times out. This could result in a unknown
resets when regulator/clocks are disabled in the CPU_DEAD path. To
prevent unknown resets, wait infinitely to enter power collapse but
throw a warning after the 1ms mark.

The platform_cpu_kill() path is also executed in the reboot path when a
core tries to stop secondary cores. In these cases, platform_cpu_kill
shouldn't wait infinitely for the secondary cores to power collapse. To
circumvent this scenario, track dying cpus as a part of the hotplug
notification and skip waiting for the core to power collpase during
reboot path.

Change-Id: I6a7fbeeea0d50b5f1fc76a02a39f161b40a67b6c
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm: Notify secure code of L2 power mode from last core only

Notify secure code L2 low power mode only if the current core is the
last core down. In certain scenarios, its possible that Linux and
secure code have different views of what a last core and could result in
secure code not invalidating a cache when the L2 was placed in a
non-retention mode.

Consider a two core scenario where Core 1 is power collapsed and Core 0
is the last core down setting L2 to be invalidated. Before Core 0 makes
the scm call, its possible that is interrupted to process a secure
interrupt. If the Core 1 wakes up in this time and decides to vote a
different L2 mode, this mode wouldn't be consistent with what Core 0
passes down to secure code when resuming from interrupt handling. In
these cases, the secure code could end up incorrectly invalidating the L2
on warmboot.

Also, the secure code and Linux should have a consistent view of what
last core down is to flush and invalidate L2. To ensure this, acquire a
remote (hardware) spinlock to serialize the last portion of the
power-collapse sequence. The remote spinlock will be released by the
secure code after it acquires its own lock to serialize the power
collapse sequence.

Change-Id: Ib5e2f360fddce558d22ce094dd7755c395c45a8c
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm: Acquire scm_handoff_lock conditionally

Acquisition of the scm_handoff_lock requires a TrustZone software
image that will release the lock. Without this, a deadlock will
occur since the lock will remain held forever.

Since this lock is only really needed if the qcom,allow-synced-levels
property is specified for the lpm-levels device, conditionally acquire
the lock based on this property. This avoid the TrustZone software
dependency when qcom,allow-synced-levels is not specified.

Change-Id: I8f8f1e4f9bdab6e70ef2a5484faba4e8ce8ac20c
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Conflicts:
	arch/arm/boot/dts/msm8974-v2-pm.dtsi

Signed-off-by: renderbroken <zkennedy87@gmail.com>
msm: pm: print active clocks before entering into pc

print out all active clocks during idle power collapse
and suspend power collapse using clock debug API

CRs-fixed: 596828
Change-Id: Ie653c02d490b80de001f61fe8320ee851bb139c7
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
msm: pm: bug in pc debug counters logic

The logic to find the location to add debug counter
for a CPU is incorrect and due to this the counter
of next CPU is corrupted. The logic is updated to
correct this.

CRs-fixed: 596773
Change-Id: I6de21bd480720d80ad9801d8a1331b6faf689b95
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
msm: lpm_levels: update suspend stats counters and time

suspend stats in the debug pm stats are not getting updated as
suspend stats in the suspend wake path is missing. This change
will add and update the suspend stats in the suspend wake path.

CRs-fixed: 536881
Change-Id: I3b47511afb75926e51e82fc83929f405404fbf07
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
msm: msm-pm: Remove outer cache functions

Remove outer cache functions to do cache maintenance
operations because all the newer targets having the
integrated cache controller and cache operations are
done by standard cache maintenance functions.

[myfluxi: Adapt to 8974/hammerhead]

Change-Id: Iaeaf5bc85ea629b89efabb1d3ea8cc9aa97f9790
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
msm: pm: Remove redundant cpu_init API

cpu_init() API setup the per-CPU stacks after cores
comes out of the low power modes. This API is not
needed after the PM driver start using the standard
ARM suspend/resume framework.

Change-Id: Ic384165e4fbc289c8338c66ebac1bb0d2bfadf8b
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
arm: msm: Rectify timeout initialization
This doesn't make sense to start timeout from 10ms
and count upto 20ms.

Initialize with 0ms to fix this.
Signed-off-by: renderbroken <zkennedy87@gmail.com>
arm: msm: Increase timeout to 2.5ms

CPU Boost of 2 ms has been increased to 2.5 ms to slightly improve performance.
So, also increase msm-pm timeout to prevent false warnings.

Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: lpm_levels: remove debug print

remove a pr_info that was added for debug purpose. This is
causing excessive logging issues.

CRs-fixed: 589307
Change-Id: I1f7bcb5282b51734cb7bf30ff933d65714445cba
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/lpm_levels.c
msm: lpm_levels: return new idle level to cpuidle framework

Need to return the new idle level to cpuidle framework
but just returned input value argument 'index' which is
not used actually at lpm_cpu_power_select().

CRs-fixed: 601636
Change-Id: Iabd182eeb4fbdc67f4e07b40a1b593471cf8cbdf
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
msm: lpm_levels: remove rpm handshake in l2_gdhs mode

Remove rpm handshake in l2_gdhs mode and adjust the
latency values for l2_gdhs mode. Add a new dt entry to
inform lpm_levels driver to send sleep votes to rpm.

CRs-fixed: 604873
Change-Id: I9eeae5fada4f84ee2ca2eb9d67707dee1adf56ac
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
msm: lpm_levels: fix incorrect mode select with next event time

Based on the next event timer value the best power mode will get
selected but there is a mismatch in calculation of selecting
the best mode. This change will fix that and selects the correct
mode based on the next wakeup time.

CRs-fixed: 611794
Change-Id: I31270e62b04e7a97afa1c9b0c45069ad82d1a9b0
Signed-off-by: Anil kumar mamidala <amami@codeaurora.org>
msm: lpm_levels: Fix incorrect computation of next wakeup time

The next event timer wakeup was incorrectly computed when the hard timer
event doesn't exist. Fix by ensuring the next wakeup is computed only
when a timer event is valid

Change-Id: I40c1f372f84d8f43b2101e37dcfb592193d4b2e0
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Build: Update Build Script
Signed-off-by: renderbroken <zkennedy87@gmail.com>
mm: Added filesystem dynamic read-ahead
 * Credits to Chad Gooldman
 * Thanks Pinkflozd for sharing this!
Signed-off-by: renderbroken <zkennedy87@gmail.com>
msm: remote_spinlock: Add support for remote_spin_lock_rlock_id()
remote_spin_lock_rlock_id() and remote_spin_unlock_rlock() are
added to acquire/release a raw remote lock (without a local
spinlock). This is useful when ownership of a lock must transfer
between different execution environments, such as when a lock is
used to guarantee atomicity of a set of actions spread across
different execution environments.

Specifically, these APIs are added to support a new lock which
must be acquired in Linux but released by TrustZone software.

Because no local spinlock is acquired, each thread must use a
different ID so that only one thread can proceed through the
lock at a time.

Support for these new APIs is presently implemented only for
SFPB locks.

Change-Id: Ifc5b1f552090051d2e975107e56e21e22df08924
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
kernel/power/powersuspend: LCD screen on/off hooks (Yank555.lu)
- add an alternative hook for screen on / off detection in the display
  pannel driver
- sleeps  ~0.1s sooner, wakes up ~1s later then autosleep
- clean up source formatting a bit (Paul Reioux)

Signed-off-by: Paul Reioux <reioux@gmail.com>

Conflicts:
	kernel/power/powersuspend.c