.gitignore correct netbeans project directories
stm32/desig: include in f4 library

The code is all there and working but simply isn't being built.
[cm3/sync] Add mutex_trylock()

Allows non-blocking use in user code.
[cm3/sync] mutex_lock now calls mutex_trylock repeatedly
ethernet: corrected typo in ethernet/phy_ksz8051mll.c to include setting the speed to 100M in case of 100M Half Duplex
Rename rcc_ppre1_frequency and rcc_ppre2_frequency

Rename rcc_ppre1_frequency and rcc_ppre2_frequency to rcc_apb1_frequency and rcc_apb2_frequency
Also add rcc_ahb_frequency (although it is not set correctly in all cases) which will be fixed by
the rcc commits later. Also fixup the only use in the library of these variables, the USART code.

And fix the typos that resulted
Make l1 generic too
Audit RTCPRE Shift and Mask Values

L0 - RTC Prescaler appears in RCC_CR, bit 20, 2 bits wide (RM0367 Rev 2)
L1 - RTC Prescaler appears in RCC_CR, bit 29, 2 bits wide (RM0038 Rev 10)
F0 - no prescaler setting (RM0091 Rev 7)
F1 - no prescaler setting (RM0041 Rev 4)
F2 - RTC Prescaler appears at RCC_CFGR, bit 16, 4 bits wide (RM0033 Rev 6)
F3 - no prescaler setting (RM0316 Rev 3)
F4 - RTC Prescaler appears at RCC_CFGR, bit 16, 4 bits wide (RM0090 Rev 8)
stm32: f4: Add FLASH_OPTCR1 definition

This is required for stm32f42xx and stm32f43xx with second bank options.
[ETH] Phy ID configurable as parameter
[ETH] Make support of ethernet for F1 family
[ETH] Make possibility to set other MAC addresses
[ETH] Provide enable/disable functions
[ETH] Initialize ethernet with specified PHY chip ID
[ETH] Make other changes in eth_init
[ETH] Some changes to eth_init
Rest of changes in PR377, this commit should be removed (BuFran)
merged bufran/pr/377 into master
Merge branch 'master' of github.com:brabo/libopencm3