Fixed invalid IMUL instruction tests

- Need to test 32-bit registers
Added test for Decoder to ensure operand-size override prefix is supported
Added support for grep to browser and Node test harnesses
Added tests for OUT instruction
Added tests for 'test' CPU instruction
Added tests for Decoder behaviour with sign-extended immediate operands
Added test for implicit SS segment register when (E)BP register is used
Added tests for 'cmp' CPU instruction
Added tests for 'mov' CPU instruction
Added tests for 'imul' CPU instruction with sign-extended immediate byte form
Added util.getParity(...) method
Added util.signExtend(...) method
Added test for 'callf' CPU instruction to ensure segment is used correctly
Added tests for 'cmp' CPU instruction's handling of flags and integration with 'ja' (or 'jnbe') instruction
Refactored to remove dependence on legacy CPU model

- Added integration tests for CPU with new Decoder model
- Added tests to capture decoder behaviour with different addressing modes
- Simplified decoder logic to remove some inefficient string operations (still more to remove though)
Added tests for 'lmsw' and 'smsw' CPU instructions
Added helper method to legacy unlazy flag class (to be factored out)
Added helper methods to legacy global table register classes (for IDTR and GDTR) - to be factored out
Added debug registers to legacy decoder (to be factored out)
Removed legacy instruction cache logic