Made FifoCc synchronous so large FIFOs can be implemented in block RAM.
Added a generic parameter to set the reset value of the HostIoToDut outputs.
+ Delayed done signal so it doesn't immediately terminate read/write control signal.
+ Delayed rmv signal to Up FIFO so the host has a chance to read the Up FIFO output before it is popped off.
+ Added shift registers to output the amount of empty and filled space in the FIFOs to the host a word
  at a time since the data bus width to the host is too small to send the counts for large FIFOs in a
  single transfer.
Added a version of HostIoComm with a Wishbone interface to the rest of the FPGA.
Merge branch 'master' of github.com:xesscorp/VHDL_Lib