align bracket
crypto: Squashed reverts to "crypto: Add support for crypto engine 5.0"
crypto: Fix QCEDEV platform data initialization.

Initialize the platform data before it is being used for bus scaling.

Change-Id: Ie41ddec08b52b44ae735469dd8f3052e3469eeff
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
crypto: Fix byte order alignment on data packets.

Crypto cipher/authentication operation yields incorrect results.
Although the operation is succesfull, the resulting data bytes
seems to be incorrect. The data input/outout needs to be
configured to be in little endian format.

The fix is to set the LITTLE ENDIAN flag in the CRYPTO_CONFIG
register, after configuring the crypto hardware registers and
prior to setting the GO_PROC register. This way, the little
endian format kicks in for the the data descriptor transfer
only, resulting in correct order in which bytes are input and
output.

Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
crypto: Align command descriptors to burst size.

According to the hardware design, Crypto Engine 5.0
hardware expects all descriptors to be burst-size
aligned for performance reasons. In the case of using
descriptors, unaligned addresses have a huge performance
impact. In this case it might cause h/w to take longer
processing times when compared to the crypto driver directly
setting the registers via processor.

Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
crypto: Removed NWD flag from intermediate descriptors.

The NWD flag had to be enabled only on the last data descriptor
and not in intermediate descriptors.

Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
crypto: Set INT flag on producer pipe.

The Crypto Engine hardware does not generate an End of Transfer (EOT)
interrupt for SHA algorithms. This issue is solved by:

 -Adding an INT flag for the last descriptor on the producer pipe.

Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
crypto: Enable AXI clock for Crypto Engine.

Currently the AXI clock is not enabled for the crypto driver.
Without this clock enabled, data will not be transferred
between the DDR and the Crypto Engine.This fix enables the
AXI clock.

Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
crypto: Set the BAM execution enviornment parameter.

Currently the BAM's execution enviornment parameter is not set.
Without setting this parameter, there would be no interrupts handled
on HLOS.

Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
crypto: Add support for sharing CE

Add pipe locking logic. Before accessing the CE HW,
lock all other pipes from accessing the same CE HW.
After the operation is complete, unblock the pipes.
The pipe pairs should also belong to the same group.

Change-Id: Ie696ad0efcb4b38c1fd43b315d468067bb3b8a1a
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
crypto: Fix HMAC failure

HMAC operation for small and large packets are failing.
This is due to 2 reason:
- Packet size set for each operation is larger than what is
  supported by the BAM hardware.
- Byte count value read after the end of the operation is of
  incorrect  byte order.
Fix is to decrease the max packet to the  max of (32KB-64) and
fix byte order when storing the byte count value from the register
dump of the results at the end of the operation.

Change-Id: Ieb91ab2ad22cb8a08a575c058b7178e532bea7d7
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
crypto: Fix CBC mode failure

Multiple back to back CBC packets encryption followed by
decryption operation is failing.  This failure is due to
incorrect CNTR IV  calculated at the end of the operation
that is used in the subsequent operation.

Fixed the value of the cntr iv for decryption mode.
The CNTR IV should point to the last  16 bytes of the
encrypted data packet.

Change-Id: Ibca400a3a34ab448e54508f4019410edaaca4977
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
crypto: msm: Fix counter IV calculation

CTR mode operation fails due to incorrect CNTR IV  returned
for large size packets.  For large packets, adding the number
of crypto blocks (16 byte chunks) to the CNTR_IV3 register
sometimes results in oevrflowing the register and hence an
incorrect value is reported back.

The counter IV for CTR/XTS mode is calculated incorrectly.
Th fix is to account for roll over scenarios. when the updated
counter value exceeds 0xFFFFFFFF.

Change-Id: I9343c520ce17871145eb9678d5fed9d718ddc089
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
crypto: msm: Fix failure on XTS mode

XTs mode of operation fails with a crash or hangs in some cases.
This failure is due to numerous reason:
- CRYPTO_XTS_DU_SIZE address is incorrect resulting
  in not setting the register correctly
- xts_du_size command list pointer was NULL. This results in
  the operation crashing due to dereferenciong of a NULL pointer
- XTS KEY register was not set correctly, resulting in
  incorrect results for encrypt/decrypt operation

After fixing the above XTS mode of operation is passing.

Change-Id: I1cfcfaf0ecae61510d3d4372c49a412d65d7bc40
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
crypto: msm: Set command descriptor size to burst size multiple

Remove dummy command elements added for the DES/DES3 CBC algorithm.
In order for proved perfromance, the  descriptor (data and command)
size sent to the BAM needs to be multiple of burst size (set to 64B).

Change-Id: If9b0cef79f15da73b18d55c24c32f4c0b7b1216a
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
crypto: msm: Add support for AES-CCM algorithm

AES-CCM  mode is currently failing due to numerous issues.
Following fixes have been made to make AES CCM  mode operations
pass:
- Initialize the hash commandlist
- Set LAST bit in ENCR_CFG register to indicate single operation
- Set AUTH_SEC_CFG register correctly  for decryption

Change-Id: I15d1e48046246e9ca7441a6214869abfa9f62edf
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
crypto: Add wait states for hash/hmac operations

Currently, hash (SHA1/256/hmac) operation occasionally results
in an incorrect hash value. This is due to the premature reading
of the AUTH_IV register done before the last SHA block is processed.
There needs to be enough delay (wait states) before the AUTH_IV
register is read to extract the hash value.

The current implementation has 2 wait states. Adding 2 more wait states
for hash operations, resolves the issue.

The wait states are calculated based on the inputs from the hardware
team with regards to the time taken to process the last block of 16
bytes of the data packet.

Change-Id: I4f9e784fbfca62d6636d87dc44c1bf9992e3b3e4
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
crypto: msm: Unlock mutex before exiting function

When an error is encountered while trying to register a BAM
device, unlock the mutex before returning with an error.

Change-Id: I71fd8c3e69cee23406992ec61aeab0191d26fb71
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
crypto: msm:  Fix failure to load both crypto modules

When the crypto driver modules, qcedev and qcrypto are both
configured to be built-in (not loadable), one of the probe
call fails.

This is due to both of them trying to register the same
CE BAM device to sps driver: both invokes "sps_register_bam_device".
BAM devices need to be registered only once.

Fix is to use a flag to indicate if the BAM device is already
registered and maintain a bam_register count for the number of
request made for this registration.

Also since we dont need to initialize the bam_register count in
the init function, the module_init/module_exit are removed

Change-Id: I1ba9a0320f049d605b4aecf013a46997f5bccfda
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
crypto:  msm: Add support for HW key

OEM specific HW key (primary  hardware key) is XPU protected by
trustzone and is not accessible by HLOS.

Only the Qualcomm specific HW key (secondary key) is made
available to HLOS. This patch removes access to OEM specific HW
key and replaces with the QC HW KEY.

Change-Id: I7a22218c4673c57d385eaaa8d445a93e7bc300f6
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>