hdl/modules/*/fmc_adc_iface.vhd: remove useless module

The sync chains module was just a sync FIFO for synchronizing
all data chanins to a single clock domain. however, this
synchronization is already done, as all channels are clock-crossed
to the same reference clock.
scripts/*/afc_scansta_cfg.svf: add SCANSTA configuration SVF

In order to program the FPGA via JTAG in the AFCs is necessary to
first configure the SCANSTA chip as a transparent bridge.