Fix array parameter values in verilog assemblies
Accomodate different AMBA bus numbers in Zynq platforms
Reduce worker build time by only building the cores that are needed

hdl/primitives/ocpi/types_body.vhd: bad indexing converting vhdl array to std_logic_vector
tools/ocpigen/include/wip.h: a more sophisticated verilog value generator function
tools/ocpigen/src/hdl-assembly.cxx: use the new better function for verilog values
tools/ocpigen/src/hdl-worker.cxx: implement the new verilog value generator function
core/container/hdl/src/BusDriver.cxx: allow for different AMBA bus numbers to be used.
hdl/devices/adcx.hdl/adcx.xml: change xml to be HdlDevice to same an extra build
hdl/devices/clkgen_ti_cdce72010.hdl/clkgen_ti_cdce72010.xml: ditto
hdl/devices/dac.hdl/dac.xml: ditto
hdl/devices/dram_v5.hdl/dram_v5.xml: ditto
hdl/devices/dram_v6.hdl/dram_v6.xml: ditto
hdl/devices/gbe.hdl/gbe.xml: ditto
hdl/devices/ocdp.hdl/ocdp.xml: ditto
tools/cdk/include/hdl/hdl-worker.mk: build verilog or vhdl core or both, based on xml tag
-- HdlWorker: only build for application assemblies (which happen to be verilog)
-- HdlDevice: only build for configuration/container assemblies (which happen to be VHDL)
-- HdlImplementation: build for both (used for "sma" among others).