FogBugz #206562-1: Removes the dwc usb driver

This commit removes the dwc usb driver in place of the community dwc2 USB
driver.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
FogBugz #206562-2: Enable the DWC2 USB driver on SOCFPGA

Get the DWC2 USB driver to work on the SOCFPGA platforms.

- Replaced udelay to an mdelay of 50 msecs as recommended by the spec.
- Correct the data toggling code to do proper data toggling for bulk
  transfers.
- Use INCR4 DMA burst that is also used in the Linux driver.
- Changed host fifo sizes to match was is recommended by the spec.
- Use CONFIG_SYS_USB_ADDRESS as the base address for the driver.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
FogBugz #206562-3: Add DWC2 OTG driver to socfpga_common

Edit the socfpga config file to include the dwc2 USB driver along with
support for ethernet and mass storage.

Tested on Cyclone5 and Arria5 devkits.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
FogBugz #207596: Fix LWH2F bridge issue when boot from FPGA

To fix the issue where the LWH2F bridge is not enabled per
handoff when boot from FPGA. This will ensure Preloader pass
the bridge handoff info to U-Boot correctly.At same time, this
patch also fixed the label duplication within lowlevel_init.S.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #205356: Increase DTB size for U-Boot QSPI boot

To increase fdtimagesize from 20kB to 28kB. Its to accommodate
the increasing size of GSRD DTB which is slightly beyond 20kB.
This is applicable for QSPI boot within U-Boot.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #206924: Fix Preloader build error when program FPGA from QSPI

To fix Preloader build error when Preloader boot from QSPI and
FPGA programming enabled.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #208110: Fix the L4 clock calculation algorithm

To fix the L4 clock calculation algorithm as the L4 divider
in value of power of 2 instead divisor itself.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #208554: RAM boot to reset Clock Manager during CSEL  0

To enable RAM boot when CSEL = 0. The RAM boot code will put
Main PLL and Peripheral to bypass mode. It will set the QSPI
and NANDSDMMC clock dividers for both PLLs to default value.
Later, the code will disable the RAM boot before triggering
warm reset. The RAM boot code is located at the last 4kB of
on-chip RAM. The purpose of this RAM boot is to overcome boot
up hang issue which due to faulty PLL.

Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v2
- Auto calculate the function size when copying the function