- removed unused variables


git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@28282 3ad0048d-3df7-0310-abae-a5850022a9f2
* m68k: partially improved code generation for comparisons.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@28283 3ad0048d-3df7-0310-abae-a5850022a9f2
Fix ARM LoadScheduler in case of Pre/PostIndexed addressing

There was an interference between the load scheduler and then
Str/LdrAdd/Sub2Str/Ldr peephole optimizer.

ldrb r0, [r2]
ldrb r1, [r2, #1]
orr r3, r0, r1
add r2, r2, #2

got changed pre-regalloc to:
ldrb r1, [r2, #1]
ldrb r0, [r2]
orr r3, r0, r1
add r2, r2, #2

and the peephole optimizer collapsed the add into the second ldrd:
ldrb r1, [r2, #1]
ldrb r0, [r2], #2
orr r3, r0, r1

Then the post-peephole optimizer changed that into:
ldrb r0, [r2], #2
ldrb r1, [r2, #1]
orr r3, r0, r1

so r1 got loaded from a modified base-register.

This patch prevents the scheduler from moving an ldr-instruction if it
uses Pre/Post-indexing and the instruction before it uses the
base-register.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@28284 3ad0048d-3df7-0310-abae-a5850022a9f2
Fix for AndLsl2Lsl in ARM Peephole optimizer

AndLsl2Lsl assigned the wrong register to the remaining instruction, and
also did not check for the register.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@28285 3ad0048d-3df7-0310-abae-a5850022a9f2