Reverse 206485.

After some discussions the preferred semantics of
the always_inline attribute is
inline always when the compiler can determine
that it it safe to do so.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206487 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: add acquire/release versions of the existing atomic intrinsics.

These will be needed to support IR-level lowering of atomic
operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206489 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: switch to IR-based atomic operations.

Goodbye code!

(Game: spot the bug fixed by the change).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206490 91177308-0d34-0410-b5e6-96231b3b80d8
ManagedStatic is never built with a null constructor, remove support for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206492 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: [su]xtw use W regs as inputs, not X regs.

Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing
mode handling.

PR19455 and rdar://16650642

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206495 91177308-0d34-0410-b5e6-96231b3b80d8
Improve ARM64 vector creation

This patch improves the performance of vector creation in caseiswhere where
several of the lanes in the vector are a constant floating point value. It
also includes new patterns to fold together some of the instructions when the
value is 0.0f. Test cases included.

rdar://16349427

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206496 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Legalize operands after changing dst reg in FixSGPRCopies

Otherwise we may not legalize some illegal REG_SEQUENCE instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206497 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Teach SIInstrInfo::moveToVALU() how to handle PHI instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206498 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Change default register class for i32 to SReg_32

SIFixSGPRCopies is smart enough to handle this now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206499 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Stop using i128 as the resource descriptor type

Having i128 as a legal type complicates the legalization phase.  v4i32
is already a legal type, so we will use that instead.

This fixes several piglit tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206500 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Add comment clariying use of sext for result of MUL_U24

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206501 91177308-0d34-0410-b5e6-96231b3b80d8
Make test/CodeGen/ARM64/vector-insertion.ll explicitly select neon syntax

Change the command line vector-insertion.ll to explicitly set the neon syntax
to apple so that buildbots that default to other syntaxes won't fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206502 91177308-0d34-0410-b5e6-96231b3b80d8
Start pushing changes for Mips Fast-Isel



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206505 91177308-0d34-0410-b5e6-96231b3b80d8
remove some dead code

 lib/Analysis/IPA/InlineCost.cpp         |   18 ------------------
 lib/Analysis/RegionPass.cpp             |    1 -
 lib/Analysis/TypeBasedAliasAnalysis.cpp |    1 -
 lib/Transforms/Scalar/LoopUnswitch.cpp  |   21 ---------------------
 lib/Transforms/Utils/LCSSA.cpp          |    2 --
 lib/Transforms/Utils/LoopSimplify.cpp   |    6 ------
 utils/TableGen/AsmWriterEmitter.cpp     |   13 -------------
 utils/TableGen/DFAPacketizerEmitter.cpp |    7 -------
 utils/TableGen/IntrinsicEmitter.cpp     |    2 --
 9 files changed, 71 deletions(-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206506 91177308-0d34-0410-b5e6-96231b3b80d8
Fix bug 19437 - Only add discriminators for DWARF 4 and above.

Summary:
This prevents the discriminator generation pass from triggering if
the DWARF version being used in the module is prior to 4.

Reviewers: echristo, dblaikie

CC: llvm-commits

Differential Revision: http://reviews.llvm.org/D3413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206507 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM64,C++11] Range'ify another loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206539 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIR

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206541 91177308-0d34-0410-b5e6-96231b3b80d8
PMBuilder: Expose an option to disable tail calls

Adds API to allow frontends to disable tail calls in PassManagerBuilder.

<rdar://problem/16050591>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206542 91177308-0d34-0410-b5e6-96231b3b80d8
Fix example for VS2012.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206544 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206547 91177308-0d34-0410-b5e6-96231b3b80d8