fdt: Add functions to query a node's #address- and #size-cells

Given a device tree node, the fdt_n_addr_cells() function will walk up
the device tree and search for an #address-cells property. It returns
the number of cells required by the device tree node to represent an
address.

Similarly the fdt_n_size_cells() function returns the number of cells
required by the given device tree node to represent a size. It achieves
that by walking up the device tree in seach for a #size-cells property.

If no #address-cells or #size-cells property can be found, both of the
functions return 1.

Signed-off-by: Thierry Reding <treding@nvidia.com>
fdt: Add a function to get the index of a string

Given a device tree node and a property name, the fdt_get_string_index()
function will look up a given string in the string list contained in the
property's value and return its index.

Signed-off-by: Thierry Reding <treding@nvidia.com>
fdt: Add resource parsing functions

Add the fdt_get_resource() and fdt_get_named_resource() functions which
can be used to parse resources (memory regions) from an FDT. A helper to
compute the size of a region is also provided.

Signed-off-by: Thierry Reding <treding@nvidia.com>
fdt: Add a function to return PCI BDF triplet

The fdtdec_pci_get_bdf() function returns the bus, device, function
triplet of a PCI device by parsing the "reg" property according to the
PCI device tree binding.

Signed-off-by: Thierry Reding <treding@nvidia.com>
fdt: Add a subnodes iterator macro

The fdt_for_each_subnode() iterator macro provided by this patch can be
used to iterate over a device tree node's subnodes. At each iteration a
loop variable will be set to the next subnode.

Signed-off-by: Thierry Reding <treding@nvidia.com>
pci: Abort early if bus does not exist

When listing the devices on a PCI bus, the current code will blindly try
to access all devices. Internally this causes pci_bus_to_hose() to be
repeatedly called and output an error message every time. Prevent this
by calling pci_bus_to_hose() once and abort early if no bus was found.

Signed-off-by: Thierry Reding <treding@nvidia.com>
pci: Honour pci_skip_dev()

When enumerating devices, honour the pci_skip_dev() function. This can
be used by PCI controller drivers to restrict which devices will be
probed.

This is required by the NVIDIA Tegra PCIe controller driver, which will
fail with a data abort exception if an access is attempted to a device
number larger than 0 outside of bus 0. pci_skip_dev() is therefore
implemented to prevent any such accesses.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Add pr_fmt() macro

This macro can be overridden in source files (before including common.h)
and can be used to specify a prefix for debug and error messages. An
example of how to use this is shown below:

	#define pr_fmt(fmt) "foo: " fmt

	#include <common.h>

	...
	debug("bar");

The resulting message will read:

	foo: bar

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Implement tegra_plle_enable()

This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Provide PCIEXCLK reset ID

This reset is required for PCIe and the corresponding ID therefore needs
to be defined.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Implement powergate support

Implement the powergate API that allows various power partitions to be
power up and down.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Implement XUSB pad controller

This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.

Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Add XUSB pad controller on Tegra124

The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA
lanes.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Enable XUSB pad controller on Jetson TK1

Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
so that the XUSB pad controller can be appropriately configured.

Signed-off-by: Thierry Reding <treding@nvidia.com>
pci: tegra: Add Tegra PCIe driver

Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Add Tegra20 PCIe device tree node

Add the device tree node for the PCIe controller found on Tegra20 SoCs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Enable PCIe on TrimSlice

The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Add Tegra30 PCIe device tree node

Add the device tree node for the PCIe controller found on Tegra30 SoCs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Enable PCIe on Beaver

The Beaver has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network device driver so that the device can
boot over the network.

In addition the board has a mini-PCIe expansion slot.

Signed-off-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: Enable PCIe on Cardhu

The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC
is available on the dock over the PCIe bus. Enable the PCIe controller
and the network device driver so that the device can boot over the
network.

Signed-off-by: Thierry Reding <treding@nvidia.com>