Dummy in basics for ARM port.

  * Added commentary for :ARM feature to base-target-features.

  * Altered feature sanity-checker to know about ARM and believe
that it is a cheneygc target (can and probably will be changed
later, but a cheneygc bringup should be easier than a gencgc
bringup).

  * Added an :ARM target mapping for source files.

  * Added dummy files for each target-specific source file in the
build process.
KLUDGE tfb/ldso-stubs.lisp to at least build for ARM.

  * This is an outright KLUDGE, and will not produce output that
survives make-target-1.  It will, however, build, and that's
sufficient to allow hacking to proceed for make-host-1.

  * At some point in the future, once the correct LDSO_STUBIFY
magic has been determined, this commit should probably be amended.
compiler/arm/parms.lisp: Lay in the most basic machine info.

  * This amounts to describing how wide a heap word is, how wide a
machine register is, and so on.

  * Also define some assembler-related parameter, for no really
good reason.

  * All constants copied from the PPC backend.
compiler/arm/parms: Set up basic heap spaces.

  * Copy in the basic linux cheneygc heap layout constants from
the PPC backend.  Also use the PPC value for linkage table entry
size, even though it will almost-certainly have to be changed
later.
compiler/arm/vm: Initial register definitions.

  * These are only the integer registers, with partitioning into
system registers, descriptor registers, and non-descriptor
registers, and definitions for arg-passing registers.  No
floating-point yet.
compiler/arm/vm: Initial storage-base definitions.

  * Cribbed from PPC, as exemplar of all non-x86oid ports (that is,
all ports with separate descriptor and non-descriptor stacks),
adjusted for the correct number of general registers and no
float-registers.
compiler/arm/vm: Swipe register R6 as LIP.

  * We're a precisely-scavenged backend, so we need an interior
pointer register...  Don't we?  Anyway, it's easiest to presume
that we do.
compiler/arm/vm: Initial storage-class definitions.

  * These are cribbed from the PPC backend, with the ZERO SC and
the floating-point-related SCs removed.
compiler/generic/primtype: Don't use floaty reg SCs on ARM.

  * Because we're passing on ARM floating-point for the time being,
we don't have SCs for the various floating-point register storage.

  * To allow the build to proceed, disable specialized storage for
floating-point values on ARM.
More ARM floating-point conditionals.

  * These disable various things that depend on the target
floating-point formats, which we have not yet defined constants
for.
compiler/arm/backend-parms: Define the "fasl implementation".

  * One of four (?) critical parameters normally set in this file,
and the first required.  Following the pattern for the other
backends, define it as the backend architecture name.
build-order.lisp-expr: Don't compile float-tran on ARM for now.

  * SYS:SRC;COMPILER;FLOAT-TRAN requires a bunch of constants for
the layout of a floating-point number to be defined, and since the
current implementation plan is to defer these details for as long
as possible, the easiest thing to do is to simply prevent the file
from being built for the time being.
compiler/arm/backend-params: Define *BACKEND-BYTE-ORDER*.

  * Crib this from the MIPS backend, which is another architecture
that can be run (and is seen in the wild to be run) in both little
and big endian modes.
compiler/arm/parms: Initial list of static-symbols and static-funs.

  * We need these in order to build SYS:SRC;COMPILER;GENERIC;UTILS.

  * Just define the baseline set of static-symbols, and an empty
set of static-funs.  The former is essentially constant over all
architectures, and the latter is in theory dependent on the actual
VOP definitions for each backend, although there is a great deal
of commonality between backends.  We can add static-funs as we
need them.
compiler/arm/insts: Initial import from older tree.

  * Copied in from an older port tree.  Contains assembler
definitions only, not disassembler definitions.
compiler/arm/macros: LOADW and STOREW.

  * Cribbed from the PPC definition, updated to use ARM
instructions (hopefully correct).
compiler/arm/vm: Swipe register R5 as CODE.

  * For various reasons of implementation simplicity, we need to
dedicate a register as reg_CODE.  We can revisit this decision
later, but it seems unlikely on the whole, even if ARM has good
program-counter-relative addressing modes.
compiler/arm/vm: Define "random" TNs for important registers.

  * This is the basic set that we seem likely to need.  Code
cribbed from the PPC port.
compiler/arm/macros: The MOVE macro (move src to dst unless src IS dst).

  * This is a common macro, found in all the backends.  This
version cribbed from the PPC backend, modulo updates for the ARM
instruction set.
compiler/arm/macros: Stack storage access macros.

  * These are LOAD-STACK-TN, STORE-STACK-TN, and
MAYBE-LOAD-STACK-TN, all cribbed from the PPC versions.