VL updates for SystemVerilog packages and better implicit wire handling

 - Added basic representation and parsing for packages.
 - Extended module/interface parsing to reject invalid elements such as module
   instances inside of interfaces, modports inside of modules, etc.
 - Fixed interface parsing to not try to add implicit wires since that
   doesn't make sense.
 - Tweaked starting location for user-defined primitives
 - Reworked make-implicit-wires and portdecl-sign to be ordinary transforms
   that happen outside of loading, toward being able to support package
   imports.
 - Minor reorganization, collected some "annotate" transforms into a new
   transforms/annotate subdirectory.
 - Other minor documentation updates

FTY: add some stronger defalist count theorems (with Sol)
untested support for replication assignment patterns
make-implicit-wires fixes
add support for imports in scopestack
extend make-implicit-wires to handle imports
Merge with sol's scopestack stuff
vl: change imports support in scopestack to better track the origin of names
Merge jaredxb into assignpats
add imports to modules and interfaces
temporary shadowcheck stuff
Merge remote-tracking branch 'remotes/solnew/assignpats'
first version of shadow check
vl systests improvements to get things working on vcs, and other assorted niceties
passes systests
vl: fix parser fast-alist problem, add wire range/size limits, and add failtests
Merge branch 'vlpkg', VL package/import support (joint work with Sol)

This branch extends VL with preliminary support for SystemVerilog constructs
including packages, imports, and assignment patterns.  Much of this involves
more comprehensive checking for sensible scope.

Other VL changes include better case statement handling, implicit wire
handling, and (reasonable) limits on wire range/sizes to avoid practical
problems with bit-blasting very large wires/replications.  The "annotate"
family of transforms have also been collected into the transforms/annotate
directory.

VL's systests have been extended with support for VCS.  (Some tests are
suppressed on VCS due to implementation differences.)  Also, a new VL failtest
directory has been added, which currently has only a single test but will
eventually have many "must fail" checks, to ensure that VL is properly
rejecting bad designs.

There are a few other minor changes, e.g., stronger defalist count theorems in
FTY.
Merge remote-tracking branch 'remotes/origin/master'