[llvm-readobj][ELF] Factor out the code retrieve ELF symbol information
(section name, section index, full name) into the separate functions.

No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210509 91177308-0d34-0410-b5e6-96231b3b80d8
Delete X86JITInfo in the subtarget destructor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210516 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: make FastISel memcpy emission more robust.

We were hitting an assert if FastISel couldn't create the load or store we
requested. Currently this happens for large frame-local addresses, though
CodeGen could be improved there.

rdar://problem/17187463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210519 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: teach FastISel how to handle offset FrameIndices

Previously we were abandonning the attempt, leading to some combination of
extra work (when selection of a load/store fails completely) and inferior code
(when this leads to a real memcpy call instead of inlining).

rdar://problem/17187463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210520 91177308-0d34-0410-b5e6-96231b3b80d8
X86: elide comparisons after cmpxchg instructions.

The C++ and C semantics of the compare_and_swap operations actually
require us to return a boolean "success" value. In LLVM terms this
means a second comparison of the output of "cmpxchg" against the input
desired value.

However, x86's "cmpxchg" instruction sets all flags for the comparison
formed, so we can skip any secondary comparison. (N.b. this isn't true
for cmpxchg8b/16b, which only set ZF).

rdar://problem/13201607

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210523 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "X86: elide comparisons after cmpxchg instructions."

This reverts commit r210523. It was committed prematurely without waiting for
review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210524 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: disallow x30 & x29 as the destination for indirect tail calls

As Ana Pazos pointed out, these have to be restored to their incoming values
before a function returns; i.e. before the tail call. So they can't be used
correctly as the destination register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210525 91177308-0d34-0410-b5e6-96231b3b80d8
Anonymous definitions in foreach blocks triggered a 'def already exists'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210526 91177308-0d34-0410-b5e6-96231b3b80d8
Refactoring in AsmWriterEmitter::EmitPrintAliasInstruction()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210527 91177308-0d34-0410-b5e6-96231b3b80d8
Condition codes AL and NV are invalid in the aliases that use
inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM).

Matching aliases based on "immediate classes", when disassembling,
wasn't previously supported, hence adding MCOperandPredicate
into class Operand, and implementing the support for it
in AsmWriterEmitter.

The parsing for those aliases was already custom, so just adding
the missing condition into AArch64AsmParser::parseCondCode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210528 91177308-0d34-0410-b5e6-96231b3b80d8
Add detection of OS X relocatable SDK to compiler-rt as a lit.util function

Clang's lit cfg already detects the currently selected SDK via
"xcrun --show-sdk-path". The same thing should be done for compiler-rt tests,
to make them work on recent OS X versions. Instead of duplicating the detection
code, this patch extracts the detection function into a lit.util method.

Patch by Kuba Brecka (kuba.brecka@gmail.com),
reviewed at http://reviews.llvm.org/D4072


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210534 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64] Emit .ident compiler version attribute.
Patch by Ana Pazos<apazos@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210535 91177308-0d34-0410-b5e6-96231b3b80d8
[PPC64LE] Recognize shufflevector patterns for little endian

Various masks on shufflevector instructions are recognizable as
specific PowerPC instructions (vector pack, vector merge, etc.).
There is existing code in PPCISelLowering.cpp to recognize the correct
patterns for big endian code.  The masks for these instructions are
different for little endian code due to the big-endian numbering
employed by these instructions.  This patch adds the recognition code
for little endian.

I've added a new test case test/CodeGen/PowerPC/vec_shuffle_le.ll for
this.  The existing recognizer test (vec_shuffle.ll) is unnecessarily
verbose and difficult to read, so I felt it was better to add a new
test rather than modify the old one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210536 91177308-0d34-0410-b5e6-96231b3b80d8
SelectionDAG: Expand SELECT_CC to SELECT + SETCC

This consolidates code from the Hexagon, R600, and XCore targets.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210539 91177308-0d34-0410-b5e6-96231b3b80d8
SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors

This prevents a future commit from regressing:

test/CodeGen/R600/setcc-equivalent.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210540 91177308-0d34-0410-b5e6-96231b3b80d8
SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC

The SelectionDAG bad a special case for ISD::SELECT_CC, where it would
allow targets to specify:

setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);

to indicate that they wanted to expand ISD::SELECT_CC for all types.
This wasn't applied correctly everywhere, and it makes writing new
DAG patterns with ISD::SELECT_CC difficult.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210541 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a bug in the Thumb1 ARM Load/Store optimizer

Previously, the basic block was searched for future uses of the base register,
and if necessary any writeback to the base register was reset using a SUB
instruction (e.g. before calling a function) just before such a use. However,
this step happened *before* the merged LDM/STM instruction was built. So if
there was (e.g.) a function call directly after the not-yet-formed LDM/STM,
the pass would first insert a SUB instruction to reset the base register,
and then (at the same location, incorrectly) insert the LDM/STM itself.

This patch fixes PR19972. Patch by Moritz Roth.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210542 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] AVX512: Add vmovntdqa

Along with the corresponding intrinsic and tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210543 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon: Expand i1 SELECT_CC

il is legal for Hexagon, so I should have marked this as Expand for
SELECT_CC when I removed setOperationAction(ISD::SELECT_CC, MVT::Other,
Expand); in r210541.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210544 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Improved target combine rules for selecting horizontal add/sub.

This patch slightly changes the algorithm introduced at revision 210477
to fix a problem where the algorithm was producing incorrect code for 
the VEX.256 encoded versions of horizontal add/sub.

For these cases, we now try to split the two 256-bit vectors into
128-bit chunks before emitting horizontal add/sub dag nodes.

Added a new test case into haddsub-2.ll.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210545 91177308-0d34-0410-b5e6-96231b3b80d8