ARM: Set bit 22 in the PL310 (cache controller) AuxCtlr register

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

This patch ensures that bit 22 is set in the l2x0_init() function if
PL310 and not rely on the platform code to specify it. It also modifies
the 'aux' variable only if the actual register is written so that the
final printk displays the real hardware value.

ST-Ericsson ID: 281924
ST-Ericsson Linux next: Already in patch tracker

Change-Id: I9175c4ca935db4072d944202741e744f55927092
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/21841
Reviewed-by: Vijaya Kumar K-1 <vijay.kilari@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/40015
Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com>