Remove the ATI_envmap_bumpmap extension

As far as I can tell, the Intel mesa driver is the only driver in the world
still supporting this legacy extension.  If someone wants to do bump
mapping, they can use shaders.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1]
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
Reviewed-by: Ian Romanick <idr@freedesktop.org> [v3]
i965/disasm: Eliminate opcode pointer.

opcode is just a pointer to opcode_descs; we may as well use that
directly.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Create an "opcode" temporary.

This saves typing brw_inst_opcode(brw, inst) everywhere.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965: Restyle brw_disasm.c.

brw_disasm.c basically wasn't following the Mesa coding style at all.
It used 4-space indent instead of 3-space, didn't cuddle braces, didn't
put function return types on a separate line, put extra spaces in
function calls (between the name and parenthesis), and a number of other
things.

This made it fairly obnoxious to work on, since my editor is configured
to follow Mesa style in the Mesa source repository.  Fixing it to follow
a consistent style now should save time dealing with it later.

These modifications were originally generated by:
$ indent -br -i3 -npcs -ce -cs -l80 --no-tabs
with some manual changes afterwards to fit our style better.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Add support for new Gen8+ register types.

While we're at it, use proper names rather than magic numbers for the
existing fields.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Improve disassembly of jump targets on Gen6+.

Previously, flow control instructions generated output like:

(+f0) if(8) 12 8  null         0x000c0008UD { align16 WE_normal 1Q };

which included a dissasembly of the register fields, even though those
are meaningless for flow control instructions---those bits are reused
for another purpose.

It also wasn't immediately obvious which number was UIP and which was
JIP.

With this patch, we instead output:

(+f0) if(8)       JIP: 8       UIP: 12      { align16 WE_normal 1Q };

which is much clearer.

The patch also introduces has_uip/has_jip helper functions which clear
up a some generation/opcode checking mess.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Properly disassemble jump targets on Gen4-5.

Previously, our dissasembly for flow control instructions looked like:

0x00000040: else(8)         ip          65540D     { align16 switch };

It didn't print InstCount properly for ELSE/ENDIF, and didn't even
attempt to disassemble PopCount.

Now it looks like:

0x00000040: else(8)         Jump: 4     Pop: 1     { align16 switch };

which is much more readable.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Mark ELSE as having UIP on Gen8+.

This makes brw_disasm.c able to disassemble ELSE instructions correctly
on Broadwell.  (gen8_disasm.c already handles this correctly.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965: Add #defines for any32h/all32h predication.

These have existed since Ivybridge.  We don't use them today, but the
Gen8+ disassembler supports them, and I'd like to use symbolic names
rather than magic numbers.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Properly disassemble all32h/any32h align1 predicates.

While we're adding things, use symbolic constants rather than magic
numbers.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Properly disassemble the "atomic" ThreadCtrl value.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Decode Broadwell's invm/rsqrtm math functions.

We don't use these yet, but we may as well disassemble them.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Actually disassemble Gen7+ URB opcodes.

I never bothered implementing the disassembler for Gen7+ URB opcodes, so
we were just disassembling them as Ironlake/Sandybridge ones.  This
looked pretty bad when running Paul's GS EndPrimitive tests, as the
"write OWord" message was decoded at ff_sync, which doesn't exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Improve disassembly of atomic messages on Haswell+.

This backports the atomic message disassembly support from
gen8_disasm.c, which additionally offers support for decoding atomic
surface read/write messages, and showing SIMD modes and other details.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Properly decode negate source modifiers on Broadwell.

This is a port of Abdiel's 6f9f916b9b042a294813ab0542390846a38739da
to brw_disasm.c.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Cut piles of duplicate swizzle printing.

Making a helper function saves us from cut and pasting this four times.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: "Handle" Gen8+ HF/DF immediate cases.

We should print something properly, but I'm not sure how to properly
print an HF, and we don't have any DFs today to test with.

This is at least better than the current Gen8 disassembler, which would
simply assert fail.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/disasm: Use Gen6+ SFID case labels.

Most developers will recognize the Gen6+ SFID names more quickly than
the Gen4-5 ones.  Given that they're the same values, just use the new
names.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Fix typo in RT UNORM write message.

The name of this message is "Render Target UNORM Write" (Sandybridge
PRM, Volume 4 Part 1, Page 210).  Drop the bogus 'c'.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
i965/disasm: Rename msg_target to SFID.

We haven't used the name "message target" in a while - there are a lot
of things called "target", and it gets confusing.  SFID ("Shared
Function ID") is the term commonly used in the modern documentation.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>