Merge branch 'master' into wirewidthtypearithnamedparams
Remove scalpels/sponges from the patient.

Remove commented-out and debug code. Simplify some expressions to
reduce differences with master branch.
Add check target to Makefile.
Initial support for zero width wires (currently, W0W).

Add W0Wtransform pass in Backend.
Allow width spec of 0 in Bits.create().
Add isSupportW0W flag to Driver.
Allow hi < lo for Extract() if Driver.isSupportW0W
Add Extract.W0Wtransform().
Allow zero width Literal with value 0 if Driver.isSupportW0W
Make Op an abstract class with parameterless constructure and provide
case classes for unary, binary, logical, and reduction operators.
Provide a depth first search function for W0Wtransforms.
Enable some trivial but previously ignored tests.
Add ZeroWidthTest which is enabled by the JVM parameter "W0W".
Update Copyright date.
Modify W0W children, not the parent node.
Cleanup for a working (limping) version.

Replace (temporarily) getWidth() with inferWidth() to avoid problems
in Reg.regMaxWidth(); actually remove 0-width nodes; support logic
operators; update tests.
preliminary W0Wtransform for Mux, type Nodes
Add Review(), replaceNode() methods, build parent list, collect testArgs, cleanup

Track node modification in W0Wtransform().
Implemenent (and use) replaceNode() method to replace one sub-tree
with another.
Set replacement node widths to 0 so they can be candidates for
replacement higher up the tree.
Attempt to optimize zero-width node replacement.
Provide single class level testArgs for StdlibSuite so we can replace
the backend easily and silence some exception handling complaints.
Fix incorrect specification of C++ backend in VerifTest.scala.
Consistify use of zero-width and ZeroWidth names.
Add more real zero-width tests and eliminate some non-tests.
Add zero-width dot test results - these need checking.
Cleanup - remove debugging println(), rename Review(), replaceNode, add more LogicalOp support, correct UnaryOp W0Wtransform.

Rename Review -> review
Rename replaceNode -> replaceTree
Delete unused otherOperand()
Move LogicalOp.W0Wtransform() to its intended UnaryOp.W0Wtransform()
Derive assertFile() name from backend.
Add comments, remove parent link in UnaryOp.W0Wtransform()
Cleanup - added comments, renamed variables to reduce confusion.
Merge branch 'master' into zerowidthwires
Merge branch 'wirewidthtypearithnamedparams' into zerowidthwires
Merge branch 'wirewidthtypearithnamedparamsrfw' into zerowidthwires

Conflicts:
	Makefile
Fix (remove) explicit width references where they're not required.
Update width usage in forceMatchingWidths(), W0Wtransform(), and review(); add newlines before end of file in test resources.

If our width is unknown but our single child's width is known, force
us to match then in Bits.forceMatchingWidths
Check for known width in Mux.W0Wtransform() and Mux.review()
Undo mistaken newline addition.
Merge branch 'master' into zerowidthwires

Conflicts:
	Makefile
	src/main/scala/Backend.scala
	src/main/scala/Driver.scala
	src/main/scala/Module.scala